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| PRELIMINARY TECHNICAL DATA = Preliminary Technical Data Complete Thermal and System Management Controller ADM1026 Chassis Intrusion Detection FEATURES Interrupt Output (SMBAlert) Up to 19 Analog Measurement Channels (Including InterReset Input, Reset Outputs nal Measurements) Thermal Interrupt (THERM) Output Up to 8 Fan Speed Measurement Channels Shutdown Mode to Minimize Power Consumption Up to 17 General-Purpose Logic I/O Pins Limit Comparison of all Monitored Values Remote Temperature Measurement with Remote Diode (Two Channels) APPLICATIONS On-Chip Temperature Sensor Network Servers and Personal Computers Analog and PWM Fan Speed Control Outputs Telecommunications Equipment 2-wire serial System Management Bus (SMBus) Test Equipment and Measuring Instruments 8K bytes on-chip E2PROM Full SMBus 1.1 support including Packet Error Checking (PEC) FUNCTIONAL BLOCK DIAGRAM ADD/ NTE STO UT SD A SC L 3.3V ST BY 3.3V M AIN G PIO 15 G PIO 14 G PIO 13 G PIO 12 G PIO 11 G PIO 10 G PIO 9 G PIO 8 V CC G PIO REG IS TE RS SE RI AL B US IN TE R FA C E R ESE T IN 3.3V M AIN RES ET G ENE RATO R R ESE T M A IN 3.3V STBY RES ET G ENE RATO R R ESE T ST B Y FAN7/G P IO 7 FAN6/G P IO 6 FAN5G PIO 5 FAN4/G P IO 4 FAN3/G P IO 3 FAN2/G P IO 2 FAN1/G P IO 1 FAN0/G P IO 0 +V B A T (0 - +4 .0V ) +5V IN (0 - +6.66V ) -12V IN (0 - -16V ) +12V IN (0 - +1 6V ) +V C C P IN (0 - +3V ) A IN 0 (0 - +3 V) A IN 1 (0 - +3 V) A IN 2 (0 - +3 V) AIN3(0 - +3 V) A IN 4 (0 - +3 V) AIN5(0 - +3 V) A IN 6 (0 - +2.5 V) A IN 7 (0 - +2.5 V) D2+/A IN 8 (0 - + 2.5V ) D2-/A IN 9 (0 - + 2.5V ) D1+ D1-/NTES TIN BAND G AP TE M P. S ENSO R BAND G AP REF ERE NCE 8-BIT A DC G PIO 16/T H E R M CO N F IG U R AT IO N RE G I S TE R S IN P UT AT T EN U AT O RS AND AN A LO G M U LT IP L EX ER TE M P E RA T UR E CO N F IG U R AT IO N RE G IS T ER AD D R ES S PO INT E R RE G IS T ER 8KBY TES E2PRO M LIM IT CO M PA R A TO R S FAN S PEE D CO UNT ER PW M RE G ISTE R AND CO N TRO L LER VA LU E A ND LIM IT RE G IS TE R S PW M IN T E RR U P T ST AT U S RE G IS TE R S CI IN T M A SK RE G IS TE R S IN T AD M 1026 IN T E RR U P T M A S KIN G TO G P IO REG IS TE RS DA C AN A LO G O U TP U T R EG IST E R AN D 8 -B IT DA C AG N D DG N D V REF (1.8 2V O R 2.5V) REV. PrP 9/01 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001 PRELIMINARY TECHNICAL DATA PRODUCT DESCRIPTION The ADM1026 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various system parameters. The ADM1026 has up to 19 analog measurement channels. Fifteen analog voltage inputs are provided, of which five are dedicated to monitoring +3.3V, +5V and 12V power supplies and the processor core voltage. The ADM1026 can monitor two further power-supply voltages by measuring its own analog and digital VCC. One input (two pins) is dedicated to a remote temperature-sensing diode. Two further pins can be configured as general-purpose analog inputs to measure 0 to 2.5V, or as a second temperature sensing input.The 8 remaining inputs are general-purpose analog inputs with a range of 0 to 2.5V or 0 to 3V. Finally, the ADM1026 has on on-chip temperature sensor. The ADM1026 has eight pins that can be configured for fan-speed measurement or as general purpose logic I/O pins. A further 8 pins are dedicated to general-purpose logic I/O. An additional pin can be configured as a general purpose I/O or as the bidirectional THERM pin. Measured values can be read out via a 2-wire serial System Management Bus, and values for limit comparisons can be programmed in over the same serial bus. The high-speed successive-approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response to any out-of-limit measurement. The ADM1026's 3V to 5.5V supply voltage range, low supply current, and serial interface make it ideal for a wide range of applications. These include hardware monitoring and protection applications in personal computers, telecommunications equipment, and office electronics. ADM1026-SPECIFICATIONS Parameter POWER SUPPLY Supply Voltage, 3.3V STBY, 3.3V MAIN Supply Current, ICC (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted) Min 3.135 Typ 3.3 1.4 1.0 Max 5.5 3.0 250 Units V mA mA A Test Conditions/Comments Interface Inactive, ADC Active ADC Inactive, DAC Active Shutdown Mode TEMP. -TO-DIGITAL CONVERTER Internal Sensor Accuracy Resolution External Diode Sensor Accuracy Resolution Remote Sensor Source Current ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error, TUE Differential Non-Linearity, DNL Power Supply Sensitivity Conversion Time (Analog Input or Int.Temp) Conversion Time (External Temperature) Input Resistance (+12V, +5V, VCCP, AIN0 - AIN5) Input Resistance of -12V pin Input Resistance (AIN6 - AIN9) Input Resistance of VBAT pin VBAT Current Drain (when measuring) VBAT Current Drain (when not measuring) ANALOG OUTPUT Output Voltage Range Total Unadjusted Error, TUE Full-Scale Error Zero Error Differential Non-Linearity, DNL Integral Non-Linearity Output Source Current Output Sink Current REFERENCE OUTPUT Output Voltage Output Voltage Line Regulation Load Regulation Short-Circuit Current Output Current Source Output Current Sink 3 1 3 1 90 5.5 o o o o C C 60 oC TD +100oC High Level Low Level C C A 2 1 1 11.38 34.13 140 10 140 97 105 16 12.06 36.18 200 200 500 100 100 % LSB %/V ms ms k k k k nA nA V % % LSB LSB LSB mA mA V V %/V V/mA mA mA mA See Note 3 See Note 4 See Note 4 See Note 3 Gives CR2032 Battery life > 10 years 0 1 2 1 2 1 1.8 2.47 1.82 2.50 TBD TBD TBD 2 2 2.5 3 3 1 IL = 2mA No Load Monotonic by Design 1.84 2.53 Bit 2 of Register 07h = 0 Bit 2 of Register 07h = 1 -2- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 Specifications (Continued) Parameter FAN RPM-TO-DIGITAL CONVERTER Accuracy Full-Scale Count FAN0 TO FAN7 Nominal Input RPM (Note 5) Min Typ Max 6 255 8800 4400 2200 1100 21.1 22.5 23.9 Units % RPM RPM RPM RPM kHz Divisor = 1, Fan Count = 153 Divisor = 2, Fan Count = 153 Divisor = 4, Fan Count = 153 Divisor = 8, Fan Count = 153 Test Conditions/Comments See Note 5 Internal Clock Frequency OPEN-DRAIN O/P'S, PWM, GPIO0-16 Output High Voltage, VOH Output Low Voltage, VOL PWM Output Frequency OPEN-DRAIN DIGITAL OUTPUTS INT, RESETMAIN, RESETSTBY) Output Low Voltage, VOL High Level Output Leakage Current, IOH RESET Pulse Width OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Leakage Current, IOH SERIAL BUS DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN0-7, GPIO0-16) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis (Fan 0 - 7) RESETMAIN, RESETSTBY RESETMAIN Threshold RESETSTBY Threshold RESETMAIN Hysteresis RESETSTBY Hysteresis DIGITAL INPUT CURRENT Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN EEPROM RELIABILITY Endurance Data Retention SERIAL BUS TIMING Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU;STA Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf 2.4 0.4 75 V V Hz IOUT = 3.0mA, VCC = 3.3V IOUT = -3.0mA, VCC = 3.3V 140 0.1 180 0.4 1 240 V A ms IOUT = -3.0mA, VCC = 3.3V VOUT = VCC 0.1 0.4 1 V A IOUT = -3.0mA, VCC = 3.3V VOUT = VCC 2.2 0.8 500 V V mV See Notes 6 and 7 VCC = 3.3V VCC = 3.3V VCC = 3.3V RESETMAIN triggered from AVCC RESETSTBY triggered from DVCC 2.4 0.8 250 2.94 3.08 60 50 -1 1 20 100 100 700 V V mV V mV mV A A pF K cycles Years VIN = VCC VIN = 0 See Note 9 See Note 10 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 See Figure 1 400 50 4.7 4.7 4 4.7 4 1000 300 kHz ns s s s s s ns s REV. PrP -3- PRELIMINARY TECHNICAL DATA ADM1026 Specifications (Continued) Parameter Data Setup Time, tSU;DAT Data Hold Time, tHD;DAT NOTES 1 2 3 Min 250 300 Typ Max Units ns ns Test Conditions/Comments See Figure 1 See Figure 1 4 5 6 7 8 9 10 All voltages are measured with respect to GND, unless otherwise specified Typicals are at TA=25C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3V TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators. VBAT input is only linear for VBAT voltages greater than 1.5V. Total analog monitoring cycle time is nominally 273ms, made up of 18 11.38ms measurements on analog input and internal temperature channels, and 2 34.13ms measurements on external temperature channels. The total fan count is based on 2 pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and the fan speed. See section on Fan Speed Monitoring for more details. ADD is a three-state input that may be pulled high, low or left open-circuit. Logic inputs will accept input high voltages up to 5V even when device is operating at supply voltages below 5V. Timing specifications are tested at logic levels of VIL = 0.8V for a falling edge and VIH = 2.1V for a rising edge. Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at -40C, 25C and 85C. Typical Endurance at 25C is 700,000 cycles. Retention lifetime equivalent at junction temperature (Tj) = 55C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure 2. ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION 4 2 G PIO 16/T H E R M Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . 6.5 V Voltage on 12V VIN Pin . . . . . . . . . . . . . . . . . . . . . . . . +20V Voltage on -12V VIN Pin . . . . . . . . . . . . . . . . . . . . . . . -20V Voltage on Analog Pins . . . . . . . . . . -0.3V to (VCC+0.3V) Voltage on Open Drain Digital Pins . . . . . . -0.3V to 6.5V Input Current at any pin . . . . . . . . . . . . . . . . . . . . . . 5mA Package Input Current . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Junction Temperature (T Jmax) . . . . . . . 150 C Storage Temperature Range . . . . . . . . . -65C to +150C Lead Temperature, Soldering Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . . . +215C Infra-Red 15 sec . . . . . . . . . . . . . . . . . . . . . . . . . +200C ESD Rating -12VIN pin . . . . . . . . . . . . . . . . . . . . . 1000 V ESD Rating all other pins . . . . . . . . . . . . . . . . . . . 2000 V *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4 1 A IN 0 (0 - 3V ) 4 0 A IN 1 (0 - 3V ) 3 9 A IN 2 (0 - 3V ) 3 8 A IN 3 (0 - 3V ) 4 6 G PIO 12 4 5 G PIO 13 4 4 G PIO 14 PIN 1 ID E N T IF IE R G PIO 9 G PIO 8 F AN 0/G P IO 0 F AN 1/G P IO 1 F AN 2/G P IO 2 F AN 3/G P IO 3 3.3V M AIN DG N D F AN 4/G P IO 4 1 2 3 4 5 6 7 8 9 3 6 A IN 5 (0 - 3V ) 3 5 A IN 6 (0 - 2.5V ) 3 4 A IN 7 (0 - 2.5V ) 3 3 V C C P (0 - 3V ) 4 8 G PIO 10 4 7 G PIO 11 4 3 G PIO 15 3 7 A IN 4 (0 - 3V ) 3 2 +12V IN (0 - 16V ) 3 1 -12V IN (0 - 16V ) 3 0 +5V IN (0 - 6.66V ) 2 9 +V B A T (0 - 4. 4V) 2 8 D2+/A IN 8 (0 - 2 .5V) 2 7 D2-/A IN 9 (0 - 2 .5V) 2 6 D1+ 2 5 D1-/NT E ST IN AD M 10 26 T O P V IE W (No t to S cale) F AN 5/G P IO 5 1 0 F AN 6/G P IO 6 1 1 F AN 7/G P IO 7 1 2 R E S ET S T B Y 1 9 AG N D 2 1 3.3V S T BY 2 2 PWM 18 DA C 2 3 IN T 1 7 THERMAL CHARACTERISTICS 48-Pin LQFP Package: JA = 50C/Watt, JC = 10C/Watt ORDERING GUIDE Temperature Range 0C to +100C Package Description 48-Pin LQFP tR t LO W Model ADM1026JST Package Option ST48 tF t HD ;S TA S CL t HIG H t HD ;S TA t HD ;D A T t S U ;D A T t S U ;S T A AD D/N TE S T O U T 1 5 R E S ET M A IN 2 0 t S U;S TO S DA tB U F P S S VREF 24 S DA 1 4 S CL 1 3 CI 1 6 P Figure 1. Diagram for Serial Bus Timing -4- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 PIN FUNCTION DESCRIPTION PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MNEMONIC GPIO9 GPIO8 FAN0/GPIO0 FAN1/GPIO1 FAN2/GPIO2 FAN3/GPIO3 3.3V MAIN DGND FAN4/GPIO4 FAN5/GPIO5 FAN6/GPIO6 FAN7/GPIO7 SCL SDA ADD/ NTESTOUT CI TYPE Digital I/O 1 Digital I/O 1 DESCRIPTION General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. Fan tachometer input, or can be re-configured as a general purpose digital I/O pin. This has an internal 10k pullup resistor to 3.3VSTBY Fan tachometer input, or can be re-configured as a general purpose digital I/O pin. This has an internal 10k pullup resistor to 3.3VSTBY Fan tachometer input, or can be re-configured as a general purpose digital I/O pin. This has an internal 10k pullup resistor to 3.3VSTBY Fan tachometer input, or can be re-configured as a general purpose digital I/O pin. This has an internal 10k pullup resistor to 3.3VSTBY Monitors the main 3.3V system supply. Does NOT power device. Ground pin for digital circuits. Fan tachometer input, or can be re-configured as a general purpose digital I/O pin. This has an internal 10k pullup resistor to 3.3VSTBY Fan tachometer input, or can be re-configured as a general purpose digital I/O pin. This has an internal 10k pullup resistor to 3.3VSTBY Fan tachometer input, or can be re-configured as a general purpose digital I/O pin. This has an internal 10k pullup resistor to 3.3VSTBY Fan tachometer input, or can be re-configured as a general purpose digital I/O pin. This has an internal 10k pullup resistor to 3.3VSTBY Open-drain Serial Bus Clock. Requires 2.2k pullup resistor. pullup resistor. Digital I/O Digital I/O Digital I/O Digital I/O Analog Input Ground Digital I/O Digital I/O Digital I/O Digital I/O Digital Input Digital I/O Digital Input Digital Input Serial Bus Data. Open-drain output. Requires 2.2k This is a three-state input that controls the two LSBs of the Serial Bus Address. It also functions as the output for NAND tree testing. An active high input which captures a Chassis Intrusion event in Bit 6 of Status Register 4. This bit will remain set until cleared, so long as battery voltage is applied to the VBAT input, even when the ADM1026 is powered off. Interrupt Request (open drain). The output is enabled when Bit 1 of the Configuration Register is set to 1. The default state is disabled. It has an on-chip 100k pullup resistor. Open drain Pulse-width modulated output for control of fan speed. This pin defaults to being high for 100% duty cycle for use with nMOS drive circuitry. If a p-MOS device is used to drive the fan the PWM output may be inverted by setting bit 1 of Test Register 1 = 1. Power-on Reset. 5 mA driver (open drain), active low output with a 180 ms typical pulse width. RESETSTBY is asserted whenever 3.3VSTBY is below the reset threshold. It remains asserted for approx. 180ms after 3.3VSTBY rises above the reset threshold. Power-on Reset. 5 mA driver (open drain), active low output with a 180 ms typical pulse width. RESETMAIN is asserted whenever 3.3V MAIN is below the reset threshold. It remains asserted for approx. 180ms after 3.3V MAIN rises above the reset threshold. If, however, 3.3V STBY rises with or before 3.3V MAIN, then RESETMAIN remains asserted for 180ms after RESETSTBY is deasserted. Pin 20 also functions as an active low RESET input. -5- 17 INT Digital Output 18 PWM Digital Output 19 RESETSTBY Digital Output 20 RESETMAIN Digital I/O REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 PIN FUNCTION DESCRIPTION (CONTINUED) PIN NO. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NOTES 1 MNEMONIC AGND 3.3V STBY DAC VREF D1-/NTESTIN D1+ D2-/AIN9 D2+/AIN8 VBAT +5VIN -12VIN +12VIN +VCCP AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 GPIO16/ THERM GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 TYPE Ground Power Supply Analog Output Analog Output Analog Input Analog Input Programmable Analog Input Programmable Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Digital I/O 1 DESCRIPTION Ground pin for analog circuits Supplies 3.3V power for the ADM1026. Also monitors 3.3V standby power rail. 0 to 2.5V output for analog control of fan speed. Reference voltage output. Can be selected as 1.8V (default) or 2.5V. Connected to cathode of 1st remote temperature sensing diode. If held high at power up it activates NAND tree test mode. Connected to anode of 1st remote temperature sensing diode. Connected to cathode of 2nd remote temperature sensing diode, or may be re-configured as a 0 - 2.5V analog input Connected to anode of 2nd remote temperature sensing diode, or may be re-configured as a 0 - 2.5V analog input Monitors battery voltage, nominally +3V. Monitors +5 V supply. Monitors -12 V supply. Monitors +12 V supply. Monitors processor core voltage (0 to 3.0V). General-purpose 0 to 2.5V analog input. General-purpose 0 to 2.5V analog input. General-purpose 0 to 3V analog input. General-purpose 0 to 3V analog input. General-purpose 0 to 3V analog input. General-purpose 0 to 3V analog input. General-purpose 0 to 3V analog input. General-purpose 0 to 3V analog input. General purpose I/O pin can be configured as a digital input or output. Can also be configured as a bidirectional THERM pin (open drain). General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. Digital I/O 1 Digital I/O 1 Digital I/O 1 Digital I/O 1 Digital I/O 1 Digital I/O 1 GPIO pins are open-drain and require external pullup resistors. -6- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 FUNCTIONAL DESCRIPTION GENERAL DESCRIPTION CHASSIS INTRUSION The ADM1026 is a complete system hardware monitor for microprocessor-based systems. The device communicates with the system via a serial System Management Bus. The serial bus controller has a hardwired address line for device selection (ADD, pin 15), a serial data line for reading and writing addresses and data (SDA, pin 14), and an input line for the serial clock (SCL, pin 13). All control and programming functions of the ADM1026 are performed over the serial bus. MEASUREMENT INPUTS A chassis intrusion input (pin 16) is provided to detect unauthorised tampering with the equipment. This event is latched in a battery-backed register bit. RESETS The ADM1026 has two power on reset outputs, RESETMAIN and RESETSTBY, that are asserted when 3.3VMAIN or 3.3VSTBY fall below the reset threshold. These give a 180ms reset pulse at power up. RESETMAIN also functions as an active-low RESET input. FAN SPEED CONTROL OUTPUTS Programmability of the analog and digital measurement inputs makes the ADM1026 extremely flexible and versatile. The device has an 8 bit A-to-D converter, and 17 analog measurement input pins that can be configured in different ways. Pins 25 and 26 are dedicated temperature inputs and may be connected to the cathode and anode of a remote temperature-sensing diode. Pins 27 and 28 may be configured as a temperature input and connected to a second temperature-sensing diode, or they may be re-configured as analog inputs with a range of 0 to +2.5V. Pins 29 to 33 are dedicated analog inputs with on-chip attenuators, configured to monitor VBAT, +5V, -12V, +12V, and the processor core voltage VCCP, respectively. Pins 34 to 41 are general-purpose analog inputs with a range of 0 to +2.5V or 0 to +3V. These are mainly intended for monitoring SCSI termination voltages, but may be used for other purposes. The ADC also accepts input from an on-chip bandgap temperature sensor that monitors system ambient temperature. Finally, the ADM1026 monitors the supply from which it is powered, 3.3VSTBY, so there is no need for a separate pin to monitor this power supply voltage. The ADM1026 has 8 pins that are general-purpose logic I/O pins (pins 1,2 and 43 to 48), a pin that can be configured as GPIO or as a bidirectional thermal interrupt (THERM) pin (pin 42) and 8 pins that can be configured for fan speed measurement or as general-purpose logic pins (pins 3 to 6 and 9 to 12). SEQUENTIAL MEASUREMENT The ADM1026 has two outputs intended to control fan speed, though they can also be used for other purposes. Pin 18 is an open-drain pulse-width modulated (PWM) output with a programmable duty-cycle and an output frequency of 75Hz. Pin 23 is connected to the output of an on-chip, 8-bit digital-to-analog converter with an output range of zero to 2.5V. Either or both of these outputs may be used to implement a temperature-controlled fan by controlling the speed of a fan dependent upon the temperature measured by the onchip temperature sensor or remote temperature sensors. INTERNAL REGISTERS OF THE ADM1026 The ADM1026 contains a large number of data registers. A brief description of the principal registers is given below. More detailed descriptions are given in the relevant sections and in the tables at the end of the data sheet. Address Pointer Register: This register contains the address that selects one of the other internal registers. When writing to the ADM1026, the first byte of data is always a register address, which is written to the Address Pointer Register. Configuration Registers: Provide control and configuration for various operating parameters of the ADM1026. Fan Divisor Registers: Contain counter pre-scaler values for fan speed measurement. DAC/PWM Control Registers: Contain speed values for PWM and DAC fan drive outputs. GPIO Configuration Registers: These configure the GPIO pins as input or output and for signal polarity. Value and Limit Registers: The results of analog voltage inputs, temperature and fan speed measurements are stored in these registers, along with their limit values. Status Registers: These registers store events from the various interrupt sources. Mask Registers: Allow masking of individual interrupt sources. EEPROM When the ADM1026 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. Measured values from these inputs are stored in Value Registers. These can be read out over the serial bus, or can be compared with programmed limits stored in the Limit Registers. The results of out of limit comparisons are stored in the Interrupt Status Registers, and will generate an interrupt on the INT line (pin 17). Any or all of the Interrupt Status Bits can be masked by appropriate programming of the Interrupt Mask Registers. The ADM1026 has 8K bytes of non-volatile, ElectricallyErasable Programmable Read-Only Memory (EEPROM), from register addresses 8000h to 9FFFh. This may be used for permanent storage of data that will not be lost when the ADM1026 is powered down, unlike the data in -7- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 the volatile registers. Although referred to as Read Only Memory, the EEPROM can be written to (as well as read from) via the serial bus in exactly the same way as the other registers. The only major differences between the E2PROM and other registers are: 1. An EEPROM location must be blank before it can be written to. If it contains data, it must first be erased. 2. Writing to EEPROM is slower than writing to RAM. 3. Writing to the EEPROM should be restricted because it has a limited write/cycle life of 100,000 write operations, due to the usual EEPROM wear-out mechanisms. The E2PROM in the ADM1026 has been qualified for two key E2PROM memory characteristics:- memory cycling endurance and memory data retention. Endurance qualifies the ability of the E2PROM to be cycled through many Program, Read and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as follows: (a) initial page erase sequence (b) read/verify sequence (c) program sequence (d) second read/verify sequence In reliability qualification, every byte is cycled from 00h to FFh until a first fail is recorded signifying the endurance limit of the E2PROM memory. Retention quantifies the ability of the memory to retain its programmed data over time. The E2PROM in the ADM1026 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (Tj = 55C). As part of this qualification procedure, the E2PROM memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the E2PROM memory is guaranteed to retain its data for its full specified retention lifetime every time the E2PROM is reprogrammed. It should be noted that retention lifetime SERIAL BUS INTERFACE based on an activation energy of 0.6eV will derate with Tj as shown in Figure 2. Figure 2. E2PROM Memory Retention Control of the ADM1026 is carried out via the serial System Management Bus (SMBus). The ADM1026 is connected to this bus as a slave device, under the control of a master device. The ADM1026 has a 7-bit serial bus slave address. When the device is powered up, it will do so with a default serial bus address. The five MSB's of the address are set to 01011, the two LSB's are determined by the logical states of pin 15 (ADD/NTESTOUT). This is a three-state input that can be grounded, connected to VCC or left opencircuit to give three different addresses. TABLE 1. ADDRESS PIN TRUTH TABLE ADD Pin GND No Connect VCC A1 0 1 0 9 A0 0 0 1 1 SCL 9 1 SDA S T AR T BY MASTER 0 1 0 1 1 A1 A0 R /W ACK. BY S LAV E D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY S LAV E F RA M E 1 S L AV E AD DR E SS 1 S CL (CO NT INU E D) 9 1 F RA M E 2 CO M M A ND C O D E 9 S DA (CO NT I NU E D) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY S LAV E D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY S LAV E STOP BY M AS T E R F RA M E 3 DA T A B YT E F RA M E N DA T A B YT E Figure 3a. General SMBus Write Timing Diagram -8- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 1 SCL 9 1 9 SDA S T AR T BY MASTER 0 1 0 1 1 A1 A0 R /W ACK. BY S LAV E D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY M AS T E R F RA M E 1 S L AV E AD DR E SS 1 S CL (CO NT INU E D) 9 1 F RA M E 2 DA T A B YT E 9 S DA (CO NT I NU E D) D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY M AS T E R D7 D6 D5 D4 D3 D2 D1 D0 NO AC K. STOP BY M AS T E R F RA M E 3 DA T A B YT E F RA M E N DA T A B YT E Figure 3b. General SMBus Read Timing Diagram If ADD is left open-circuit the default address will be 0101110. ADD is sampled only at power-up, so any changes made while power is on will have no immediate effect. The facility to make hardwired changes to device address allows the user to avoid conflicts with other devices sharing the same serial bus, for example if more than one ADM1026 is used in a system. GENERAL SMBUS TIMING Figures 3a and 3b show timing diagrams for general read and write operations using the SMBus. The SMBus specification defines specific conditions for different types of read and write operation, which are discussed later. The general SMBus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA whilst the serial clock line SCL remains high. This indicates that a data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. If the R/W bit is a 0 then the master will write to the slave device. If the R/W bit is a 1 the master will read from the slave device. 2. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge Bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. If the operation is a write operation, the first data byte REV. PrP after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will release the SDA line during the low period before the 9th clock pulse, but the slave device will not pull it low. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition. Note: If it is required to perform several read or write operations in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. SMBUS PROTOCOLS FOR RAM AND EEPROM The ADM1026 contains volatile registers (RAM) and non-volatile EEPROM. RAM occupies address locations from 00h to 6Fh, whilst EEPROM occupies addresses from 8000h to 9FFFh. Data can be written to and read from both RAM and EEPROM as single data bytes and as block (sequential) read or write operations of 32 data bytes, which is the maximum block size allowed by the SMBus specification. Data can only be written to unprogrammed EEPROM locations. To write new data to a programmed location it is first necessary to erase it. EEPROM erasure cannot be done at the byte level; the EEPROM is arranged as 128 pages* of 64 bytes, and an entire page must be erased. The EEPROM has three RAM registers associated with it, -9- PRELIMINARY TECHNICAL DATA ADM1026 EEPROM Registers 1, 2 and 3 at addresses 06h, 0Ch and 13h. EEPROM Registers 1 and 2 are for factory use only. EEPROM Register 3 is used to set up the EEPROM operating mode. Setting bit 0 of EEPROM Register 3 puts the EEPROM into Read Mode. Setting bit 1 puts it into Programming Mode. Setting Bit 2 puts it into Erase Mode. One, and only one of these bits must be set before the EEPROM may be accessed, setting no bits or more than one of them will cause the device to respond with No Acknowledge if an EEPROM read, program or erase operation is attempted. It is important to distinguish between SMBus write operations such as sending an address or command, and EEPROM programming operations. It is possible to write an EEPROM address over the SMBus whatever the state of EEPROM register 3. However, EEPROM Register 3 must be correctly set before a subsequent EEPROM operation can be performed. For example, when reading from the EEPROM, bit 0 of EEPROM Register 3 can be set, even though SMBus write operations are required to set up the EEPROM address for reading. Bit 3 of EEPROM Register 3 is used for EEPROM write protection. Setting this bit will prevent accidental programming or erasure of the EEPROM. If a an EEPROM write or erase operation is attempted with this bit set, the ADM1026 will respond with No Acknowledge. This bit is write once and can only be cleared by power-on reset. EEPROM Register bit 7 is used for clock extend. Programming an EEPROM byte takes approximately 250s, which would limit the SMBus clock for repeated or block write operations. Since EEPROM block read/write access is slow, it is recommended that this Clock Extend bit normally be set to 1. This allows the ADM1026 to pull SCL low and extend the clock pulse when it cannot accept any more data. *Although the EEPROM is arranged into 128 pages, only 124 pages are available to the user. The last 4 pages are reserved for manufacturing purposes and cannot be erased/ rewritten. ADM1026 WRITE OPERATIONS 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master asserts a STOP condition on SDA and the transaction ends. In the ADM1026, the send byte protocol is used to write a register address to RAM for a subsequent single byte read from the same address or block read or write starting at that address. This is illustrated in Figure 4a. 1 2 3 4 5 6 RAM S LAV E S WA ADDRE S S AP ADDRE S S (00h TO 6Fh) Figure 4a. Setting A RAM Address For Subsequent Read If it is required to read data from the RAM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read, block read or block write operation, without asserting an intermediate stop condition. Write Byte/Word In this operation the master device sends a command byte and one or two data bytes to the slave device, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code. 5. The slave asserts ACK on SDA. 6. The master sends a data byte. 7. The slave asserts ACK on SDA. 8. The master sends a data byte (or may assert STOP at this point). 9. The slave asserts ACK on SDA. 10.The master asserts a STOP condition on SDA to end the transaction. In the ADM1026, the write byte/word protocol is used for four purposes. The ADM1026 knows how to respond by the value of the command byte and EEPROM register 3. 1. Write a single byte of data to RAM. In this case the command byte is the RAM address from 00h to 6Fh and the (only) data byte is the actual data. This is illustrated in Figure 4b. 1 2 3 4 5 6 7 8 The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1026 are discussed below. The following abbreviations are used in the diagrams: S P R W A A START STOP READ WRITE ACKNOWLEDGE NO ACKNOWLEDGE S L AV E S W AD DR E S S RA M A A DA T A A P AD DR E S S (00h T O 6F h ) The ADM1026 uses the following SMBus write protocols: Send Byte In this operation the master device sends a single command byte to a slave device, as follows: Figure 4b. Single Byte Write To RAM 2. Set up a two byte EEPROM address for a subsequent read or block read. In this case the command byte is -10- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 the high byte of the EEPROM address from 80h to 9Fh. The (only) data byte is the low byte of the EEPROM address. This is illustrated in Figure 4c. 1 2 3 4 5 6 7 8 2. The master sends the 7-bit slave address followed by the write bit (low). 3. The addressed slave device asserts ACK on SDA. 4. The master sends a command code that tells the slave device to expect a block write. The ADM1026 command code for a block write is A0h (10100000). 5. The slave asserts ACK on SDA. 6. The master sends a data byte (20h) that tells the slave device 32 data bytes will be sent to it. The master should always send 32 data bytes to the ADM1026. 7. The slave asserts ACK on SDA. 8. The master sends 32 data bytes. 9.The slave asserts ACK on SDA after each data byte. 10. The master sends a PEC (Packet Error Checking) byte. 11. The ADM1026 checks the PEC byte and issues an ACK if correct. If incorrect (NACK), the master should resend the data bytes. 12. The master asserts a STOP condition on SDA to end the transaction. 1 2 3 4 5 6 7 8 9 10 11 12 S S L AV E W AD DR E S S E E P RO M E E P RO M AD DR E S S AD DR E S S A A AP HIG H BY T E L O W BY T E (80h TO 9F h) (00h TO F F h) Figure 4c. Setting An EEPROM Address If it is required to read data from the EEPROM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read, block read or block write operation, without asserting an intermediate stop condition. In this case bit 0 of EEPROM Register 3 should be set. 3. Erase a page of EEPROM memory. EEPROM memory can be written to only if it is unprogrammed. Before writing to one or more EEPROM memory locations that are already programmed, the page or pages containing those locations must first be erased. EEPROM memory is erased by writing an EEPROM page address plus an arbitrary byte of data with bit 2 of EEPROM Register 3 set to 1. As the EEPROM consists of 128 pages of 64 bytes, the EEPROM page address consists of the EEPROM address high byte (from 80h to 9Fh) and the two MSB's of the low byte. The lower 6 bits of the EEPROM address low byte only specify addresses within a page and are ignored during an erase operation. 1 2 S L AV E W AD DR E SS 3 4 5 6 7 8 9 10 E E P RO M E E P RO M AD DR E SS AD DR E SS AR BIT RA RY A P A A HIG H BY T E L O W BY T E DA T A (80h TO 9Fh ) (00h TO F F h) S COMMAND A0h BYTE SLAVE DATA A WA A DATA 1 A DATA 2 A A PEC A P (BLOCK WRITE) COUNT ADDRESS 32 Figure 4f. Block Write To EEPROM Or RAM When performing a block write to EEPROM, bit 1 of EEPROM Register 3 must be set. Unlike some EEPROM devices which limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to EEPROM, except: 1. There must be at least 32 locations from the start address to the highest EEPROM address (9FFF), to avoiding writing to invalid addresses. 2. If the addresses cross a page boundary, both pages must be erased before programming. ADM1026 READ OPERATIONS S A Figure 4d. EEPROM Page Erasure Page erasure takes approximately 20ms. If the EEPROM is accessed before erasure is complete, it will respond with No Acknowledge. 4. Write a single byte of data to EEPROM. In this case the command byte is the high byte of the EEPROM address from 80h to 9Fh. The first data byte is the low byte of the EEPROM address and the second data byte is the actual data. Bit 1 of EEPROM Register 3 must be set. This is illustrated in Figure 4e. 1 2 S L AV E W AD DR E S S 3 4 5 6 7 8 9 10 E E P RO M E E P RO M AD DR E S S AD DR E S S A A A DA T A A P HIG H BY T E L O W BY T E (80h TO 9Fh ) (00h TO F F h) The ADM1026 uses the following SMBus read protocols: RECEIVE BYTE In this operation the master device receives a single byte from a slave device, as follows: 1.The master device asserts a START condition on SDA. 2.The master sends the 7-bit slave address followed by the read bit (high). 3.The addressed slave device asserts ACK on SDA. 4.The master receives a data byte. 5.The master asserts NO ACK on SDA. 6.The master asserts a STOP condition on SDA and the transaction ends. In the ADM1026, the receive byte protocol is used to read a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or -11- S Figure 4e. Single Byte Write To EEPROM Block Write In this operation the master device writes a block of data to a slave device. The start address for a block write must previously have been set. In the case of the ADM1026 this is done by a Send Byte operation to set a RAM address or a Write Byte/Word operation to set an EEPROM address. 1. The master device asserts a start condition on SDA. REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 write byte/word operation. This is illustrated in Figure 4g. When reading from EEPROM, Bit 0 of EEPROM register 3 must be set. 1 S 2 S LAV E R ADDRE S S 3 A 4 DAT A 5 A 6 P Note: Although the ADM1026 supports Packet Error Checking (PEC), its use is optional. The PEC byte is calculated using CRC-8. The Frame Check Sequence (FCS) conforms to CRC-8 by the polynomial:C(x) = x8 + x2 + x1 + 1 Consult SMBus 1.1 specification for more information. MEASUREMENT INPUTS Figure 4g. Single Byte Read From EEPROM Or RAM BLOCK READ In this operation the master device reads a block of data from a slave device. The start address for a block read must previously have been set. In the case of the ADM1026 this is done by a Send Byte operation to set a RAM address, or a Write Byte/Word operation to set an EEPROM address. The block read operation itself consists of a Send Byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows: 1.The master device asserts a START condition on SDA. 2.The master sends the 7-bit slave address followed by the write bit (low). 3.The addressed slave device asserts ACK on SDA. 4.The master sends a command code that tells the slave device to expect a block read. The ADM1026 command code for a block read is A1h (10100001). 5.The slave asserts ACK on SDA. 6.The master asserts a repeat start condition on SDA. 7.The master sends the 7-bit slave address followed by the read bit (high). 8.The slave asserts ACK on SDA. 9.The ADM1026 sends a byte count data byte that tells the master how many data bytes to expect. The ADM1026 will always return 32 data bytes (20h), which is the maximum allowed by the SMBus 1.1 specification. 10. The master asserts ACK on SDA. 11. The master receives 32 data bytes. 12. The master asserts ACK on SDA after each data byte. 13. The ADM1026 issues a PEC byte to the master. The master should check the PEC byte and issue another block read if the PEC byte is incorrect. 14. A NACK is generated after the PEC byte to signal the end of the read. 15. The master asserts a STOP condition on SDA to end the transaction. 1 S 2 3 4 56 7 8 9 10 11 12 SLAVE WA ADDRESS CO M MAND A1h BYTE SLAVE AS RA A DATA 1 A (BLO CK RE AD ) CO UN T ADDRESS 13 DAT A 32 A 14 15 P The ADM1026 has 17 external analog measurement pins, which can be configured to perform various functions. It also measures two supply voltages, 3.3V MAIN and 3.3V STBY, and the internal chip temperature. Pins 25 and 26 are dedicated to remote temperature measurement, whilst pins 27 and 28 can be configured as analog inputs with a range of 0 to +2.5V or as inputs for a second remote temperature sensor. Pins 29 to 33 are dedicated to measuring VBAT, +5V, -12V, +12V supplies and the processor core voltage VCCP. The remaining analog inputs, pins 34 to 41 are generalpurpose analog inputs with a range of 0 to +2.5V (pins 34 and 35) or 0 to +3V (pins 36 to 41). A TO D CONVERTER These inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution of 8 bits. The basic input range is zero to +2.5V, which is the input range of AIN6 to AIN9, but five of the inputs have built-in attenuators to allow measurement of VBAT, +5V, -12V, +12V and the processor core voltage VCCP, without any external components. To allow for the tolerance of these supply voltages, the A to D converter produces an output of 3/4 full-scale (decimal 192) for the nominal input voltage, and so has adequate headroom to cope with overvoltages. Table 2 shows the input ranges of the analog inputs and output codes of the A to D converter. When the ADC is running, it samples and converts an analog or local temperature input every 711s (typical value). Each input is measured 16 times and the measurements averaged to reduce noise, so the total conversion time for each input is 11.38ms. Measurements on the remote temperature (D1 and D2) inputs take 2.13ms. These are also measured 16 times and averaged, so the total conversion time for a remote temperature input is 34.13ms. INPUT CIRCUITS PE C A Figure 4h. Block Read From EEPROM or RAM When block reading from EEPROM, bit 0 of EEPROM register 3 must be set. The internal structure for the analog inputs are shown in Figure 5. Each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a firstorder lowpass filter which gives the input immunity to high frequency noise. The -12V input also has a resistor connected to the on-chip reference to offset the negative voltage range so that it is always positive and can be handled by the ADC. The VBAT input allows the condition of a battery such as a CMOS backup battery to be monitored. To reduce current drain from the battery, the lower resistor of the VBAT attenuator is not connected, except when a VBAT measurement is being made. The total -12- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 2. A/D OUTPUT CODE VS. VIN Input Voltage +12VIN <0.0625 0.062 - 0.125 0.125 - 0.187 0.188 - 0.250 0.250 - 0.313 0.313 - 0.375 0.375 - 0.438 0.438 - 0.500 0.500 - 0563 A/D Output VCCP <0.012 0.012 - 0.023 0.023 - 0.035 0.035 - 0.047 0.047 - 0.058 0.058 - 0.070 0.070 - 0.082 0.082 - 0.094 0.094 - 0.105 -12VIN <-15.928 +5V IN <0.026 3.3VMAIN 3.3VSTBY <0.0172 V BAT <0.016 0.016 - 0.031 0.031 - 0.047 0.047 - 0.063 0.063 - 0.077 0.077 - 0.093 0.093 - 0.109 0.109 - 0.125 0.125 - 0.140 l l l AIN (0-5) <0.012 0.012 - 0.023 0.023 - 0.035 0.035 - 0.047 0.047 - 0.058 AIN(6-9) <0.010 0.010 - 0.019 0.019 - 0.029 0.029 - 0.039 0.039 - 0.049 Decimal 0 1 2 3 4 5 6 7 8 Binary 00000000 00000001 00000010 00000011 00000100 00000101 00000110 00000111 00001000 -15.928 -15.855 0.026 - 0.052 0.017 - 0.034 -15.855 -15.783 0.052 - 0.078 0.034 - 0.052 -15.783 -15.711 0.078 - 0.104 0.052 - 0.069 -15.711 -15.639 0.104 - 0.130 0.069 - 0.086 -15.639 -15.566 0.130 - 0.156 0.086 - 0.103 -15.566 -15.494 0.156 - 0.182 0.103 - 0.120 -15.494 15.422 0.182 - 0.208 0.120 - 0.138 -15.422 -15.349 0.208 - 0.234 0.138 - 0.155 0.058 - 0.070 0.049 - 0.058 0.070 - 0.082 0.082 - 0.094 0.094 - 0.105 0.058 - 0.068 0.068 - 0.078 0.078 - 0.087 4.000 - 4.063 -11.375 -11.303 1.665 - 1.691 1.110 - 1.127 1.000 - 1.040 l l l 0.750 - 0.780 0.750 - 0.780 0.625 - 0.635 64 (1/4-scale) 01000000 8.000 - 8.063 -6.750 -6.678 3.330 - 3.560 2.220 - 2.237 2.000 - 2.016 l l l 1.500 - 1.512 1.500 - 1.512 1.250 - 1.260 128 (1/2-scale) 10000000 12.000 - 12.063 -2.125 -2.053 4.995 - 5.021 3.330 - 3.347 3.000 - 3.016 l l l 2.250 - 2.262 2.250 - 2.262 1.875 - 1.885 192 (3/4 scale) 11000000 15.313 - 15.375 15.375 - 15.437 15.437 - 15.500 15.500 - 15.563 15.562 - 15.625 15.625 - 15.688 15.688 - 15.750 15.750 - 15.812 15.812 - 15.875 15.875 - 15.938 >15.938 1.705 1.777 1.777 1.850 1.850 1.922 1.922 1.994 1.994 2.066 2.066 2.139 2.139 2.211 2.211 2.283 2.283 2.355 2.355 2.428 >2.428 6.374 - 6.400 4.249 - 4.267 6.400 - 6.426 4.267 - 4.284 6.426 - 6.452 4.284 - 4.301 6.452 - 6.478 4.301 - 4.319 6.478 - 6.504 4.319 - 4.336 6.504 - 6.530 4.336 - 4.353 6.530 - 6.556 4.353 - 4.371 6.556 - 6.582 4.371 - 4.388 6.582 - 6.608 4.388 - 4.405 6.608 - 6.634 4.405 - 4.423 >6.634 >4.423 3.828 - 3.844 3.844 - 3.860 3.860 - 3.875 3.875 - 3.890 3.890 - 3.906 3.906 - 3.921 3.921 - 3.937 3.937 - 3.953 3.953 - 3.969 3.969 - 3.984 >3.984 2.871 - 2.883 2.883 - 2.895 2.895 - 2.906 2.906 - 2.918 2.918 - 2.930 2.930 - 2.941 2.941 - 2.953 2.953 - 2.965 2.965 - 2.977 2.977 - 2.988 >2.988 2.871 - 2.883 2.883 - 2.895 2.895 - 2.906 2.906 - 2.918 2.918 - 2.930 2.930 - 2.941 2.941 - 2.953 2.953 - 2.965 2.965 - 2.977 2.977 - 2.988 >2.988 2.392 - 2.402 2.402 - 2.412 2.412 - 2.422 2.422 - 2.431 2.431 - 2.441 2.441 - 2.451 2.451 - 2.460 2.460 - 2.470 2.470 - 2.480 2.480 - 2.490 >2.490 245 246 247 248 249 250 251 252 253 254 255 11110101 11110110 11110111 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 REV. PrP -13- PRELIMINARY TECHNICAL DATA ADM1026 current drain on the VBAT pin is 105nA typical (for a maximum VBAT voltage = 4V) so a CR2032 CMOS battery will function in a system in excess of the expected 10 years. Note that when a measurement is not being made of VBAT the current drain is reduced to 16nA typical. Under normal operating conditions, all measurements are made in a round-robin format, and each measurement result is actually 16 digitally averaged measurements. Averaging is not carried out on the VBAT measurement to reduce measurement time and hence reduce the current drain from the battery. The VBAT current drain when a measurement is being made is calculated by: I = (VBAT/100k) *(TPULSE/TPERIOD) For VBAT = 3V; I = (3/100k) * (711s/273ms) = 78nA TPULSE = VBAT measurement time = 711s typical TPERIOD = Time to measure all analog inputs = 273ms typical 23.3k8 A IN 0 - A IN 5 (0 - 3 V) 116.7k8 25 p F V IN SETTING OTHER INPUT RANGES AIN0 to AIN9 can easily be scaled to voltages other than 2.5V or 3V. If the input voltage range is zero to some positive voltage, then all that is required is an input attenuator, as shown in Figure 6. However, when scaling AIN0 to AIN5, it should be noted that these inputs already have an on-chip attenuator, as their primary function is to monitor SCSI termination voltages. This attenuator will load any external attenuator. The input resistance of the on-chip attenuator can be between 100k and 200k . For this tolerance not to affect the accuracy, the output resistance of the external attenuator should be very much lower than this, e.g. 1k in order to add not more than 1% to the TUE. Alternatively, the input can be buffered using an op-amp. R1 A IN(0 -9) R2 Figure 6. Scaling AIN(0 - 9) 80k8 AIN 6 - A IN9 (0 - 2.5V ) 10p F R1/R2 = (Vfs-3.0)/3.0 (for AIN0 to AIN5) R1/R2 = (Vfs-2.5)/2.5 (for AIN6 to AIN9) Negative and bipolar input ranges can be accommodated by using a positive reference voltage to offset the input voltage range so that it is always positive. 35p F 122.2k8 +1 2 V 22.7k8 To monitor a negative input voltage, an attenuator can be used as shown in Figure 7. +VOS MUX VR EF 18.9k8 1 2 1 .1k8 -12V 10p F 91.6k8 +5 V 55.2k8 25p F VIN R1 R2 AIN (0 - 9) 61.1k8 V BAT 78.8k8 *S EE T E X T 25p F Figure 7. Scaling and Offsetting AIN(0 - 9) for Negative Inputs This offsets the negative voltage so that the ADC always sees a positive voltage. R1 and R2 are chosen, so that the ADC input voltage is zero when the negative input voltage is at its maximum (most negative) value, i.e. R1/R2 = |VFS-|/VOS This is a simple and cheap solution, but the following point should be noted. 1. Since the input signal is offset but not inverted, the input range is transposed. An increase in the magnitude of the negative voltage (going more negative), will cause the input voltage to fall and give a lower output code from the ADC. Conversely, a decrease in the -14- REV. PrP 23.3k8 +V C C P 116.7k8 50p F Figure 5. Structure of Analog Inputs PRELIMINARY TECHNICAL DATA ADM1026 magnitude of the negative voltage will cause the ADC code to increase. The maximum negative voltage corresponds to zero output from the ADC. This means that the upper and lower limits will be transposed. 2. For the ADC output to be full-scale when the negative voltage is zero, VOS must be greater than the full-scale voltage of the ADC, because VOS is attenuated by R1 and R2. If VOS is equal to or less than the full-scale voltage of the ADC the input range is bipolar, but not necessarily symmetrical. This is only a problem if the ADC output must be fullscale when the negative voltage is zero. Symmetrical bipolar input ranges can easily be accommodated by making VOS equal to the full-scale voltage of the analog input and adding a third resistor to set the positive full-scale. +V O S REFERENCE OUTPUT The on-chip reference voltage is scaled and buffered at pin 24 to provide a 1.82V or 2.5V reference. This output can source or sink a load current of 2mA. The reference voltage is set to 1.82V if bit 2 of Configuration Register 3 (address 07h) is 0, 2.5V if it is 1. The voltage reference output can be used to provide a stable reference voltage to external circuitry such as LDO's. TEMPERATURE MEASUREMENT SYSTEM LOCAL TEMPERATURE MEASUREMENT R2 R1 V IN A IN(0 - 9) The ADM1026 contains an on-chip bandgap temperature sensor, whose output is digitized by the on-chip ADC. The temperature data is stored in the Local Temperature Value Register (address 1Fh). As both positive and negative temperatures can be measured, the temperature data is stored in two's complement format, as shown in Table 3. Theoretically, the temperature sensor and ADC can measure temperatures from -128oC to +127oC with a resolution of 1oC. However, temperatures below TMIN and above TMAX are outside the operating temperature range of the device, so local temperature measurements outside this range are not possible. Temperature measurement from -128oC to +127oC is possible using a remote sensor. REMOTE TEMPERATURE MEASUREMENT R3 Figure 8. Scaling and Offsetting AIN(0 - 9) for Bipolar Inputs The ADM1026 can measure the temperature of two remote diode sensors or diode-connected transistors, connected to pins 25 and 26 or 27 and 28. Pins 25 and 26 are a dedicated temperature input channel. Pins 27 and 28 can be configured to measure a diode sensor by clearing bit 3 of Configuration Register 1 (address 00h) to 0. If this bit is 1 then pins 27 and 28 are AIN8 and AIN9. The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about -2mV/oC.Unfortunately, the absolute value of Vbe, varies from device to device, and individual calibration is required to null this out, so the technique is unsuitable for mass-production. R1/R2 = |VFS-|/VOS (R3 has no effect as the input voltage at the device pin is zero when VIN = minus full-scale) R1/R3 = (VFS+-3.0)/3.0 (for AIN0 to AIN5) R1/R3 = (VFS+-2.5)/2.5 (for AIN6 to AIN9) (R2 has no effect as the input voltage at the device pin is equal to VOS when VIN = plus full-scale). V DD I NxI I B IA S D+ V O UT+ TO A D C R E M O TE S E N S IN G TR A N S IS T O R DBIAS DIO D E V O UTLO W P A S S F IL TE R f c = 65 k H z Figure 9. Signal Conditioning for Remote Diode temperature Sensors REV. PrP -15- PRELIMINARY TECHNICAL DATA ADM1026 The technique used in the ADM1026 is to measure the change in Vbe when the device is operated at two different currents. This is given by: Vbe = KT/q x ln(N) where: K is Boltzmann's constant q is charge on the carrier T is absolute temperature in Kelvins N is ratio of the two currents Figure 9 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor such as a 2N3904. If a discrete transistor is used, the collector will not be grounded, and should be linked to the base. If a PNP transistor is used the base is connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input. TABLE 3. TEMPERATURE DATA FORMAT LAYOUT CONSIDERATIONS and to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a DC voltage proportional to Vbe. This voltage is measured by the ADC to give a temperature output in 8-bit two's complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. A remote temperature measurement takes nominally 2.14ms. The results of external temperature measurements are stored in 8 bit, twos-complement format, as illustrated in Table 3. Digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. The following precautions should be taken: 1. Place the ADM1026 as close as possible to the remote sensing diode. Provided that the worst noise sources such as clock generators, data/address buses and CRTs are avoided, this distance can be 4 to 8 inches. 2. Route the D+ and D- tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible. 3. Use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended. GND 10 mil. 10 mil. D+ 10 mil. 10 mil. Temperature -128 C -125 C -100 C -75 C -50 C -25 C -10 oC 0 C +10 C +25 C +50 C +75 C +100 C +125 C +127 C Digital Output 1000 0000 1000 0011 1001 1100 1011 0101 1100 1110 1110 0111 11110110 0000 0000 0000 1010 0001 1001 0011 0010 0100 1011 0110 0100 0111 1101 0111 1111 D- 10 mil. 10 mil. GND 10 mil. Figure 10. Arrangement of Signal Tracks 4. Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/ solder joints are used, make sure that they are in both the D+ and D- path and at the same temperature. Thermocouple effects should not be a major problem as 1oC corresponds to about 240V, and thermocouple voltages are about 3V/oC of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200V. 5. Place a 0.1F bypass capacitor close to the ADM1026. 6. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. This will work up to about 6 to 12 feet. 7. For really long distances (up to 100 feet) use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D- and the shield to GND close to the ADM1026. Leave the remote end -16- REV. PrP To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input. To measure Vbe, the sensor is switched between operating currents of I and N x I. The resulting waveform is passed through a 65kHz lowpass filter to remove noise, PRELIMINARY TECHNICAL DATA ADM1026 of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed. Cable resistance can also introduce errors. 1 tance introduces about 0.5oC error. LIMIT VALUES is measured 16 times and averaged to reduce noise. The total monitoring cycle time for voltage and temperature inputs is therefore nominally: (18 16 0.711) + (2 16 2.13) = 273ms The ADC uses the internal 22.5kHz clock, which has a tolerance of 6%, so the worst case monitoring cycle time is 290ms. The fan speed measurement uses a completely separate monitoring loop, as described later. INPUT SAFETY series resis- Limit values for analog measurements are stored in the appropriate limit registers. In the case of voltage measurements, high and low limits can be stored so that an interrupt request will be generated if the measured value goes above or below acceptable values. In the case of temperature, a Hot Temperature or High Limit can be programmed, and a Hot Temperature Hysteresis or Low Limit, which will usually be some degrees lower. This can be useful as it allows the system to be shut down when the hot limit is exceeded, and re-started automatically when it has cooled down to a safe temperature. ANALOG MONITORING CYCLE TIME Scaling of the analog inputs is performed on chip, so external attenuators are normally not required. However, since the power supply voltages will appear directly at the pins, its is advisable to add small external resistors (e.g. 500) in series with the supply traces to the chip to prevent damaging the traces or power supplies should an accidental short such as a probe connect two power supplies together. As the resistors will form part of the input attenuators, they will affect the accuracy of the analog measurement if their value is too high. The worst such accident would be connecting -12V to +12V - a total of 24V difference, with the series resistors this would draw a maximum current of approx. 24mA. REFERENCE OUTPUT The analog monitoring cycle begins when a one is written to the Start Bit (bit 0), and a zero to the INT_Clear Bit (bit 2) of the Configuration Register. INT_Enable (Bit 1) should be set to one to enable the INT output. The ADC measures each analog input in turn, starting with remote temperature channel 1 and ending with local temperature. As each measurement is completed the result is automatically stored in the appropriate value register. This "round-robin" monitoring cycle continues until it is disabled by writing a 0 to bit 0 of the Configuration Register. As the ADC will normally be left to free-run in this manner, the time taken to monitor all the analog inputs will normally not be of interest, as the most recently measured value of any input can be read out at any time. For applications where the monitoring cycle time is important, it can easily be calculated. The total number of channels measured is: 5 dedicated supply voltage inputs 10 general purpose analog inputs 3.3VMAIN 3.3VSTBY Local temperature 2 remote temperature Pins 28 and 27 are measured both as analog inputs AIN8/ AIN9 and as remote temperature input D2+/D2-, irrespective of which configuration is selected for these pins. If pins 28 and 27 are configured as AIN8/AIN9, the measurements for these channels are stored in registers 27h and 29h and the invalid temperature measurement is discarded. On the other hand, if pins 28 and 27 are configured as D2+/D2-, the temperature measurement is stored in register 29h and there will be no valid result in register 27h. As mentioned previously, the ADC performs a conversion every 711s on the analog and local temperature inputs and every 2.13ms on the remote temperature inputs. Each input REV. PrP The ADM1026 has a buffered reference voltage output (pin 24), which can be programmed to 1.82V or 2.5V by clearing or setting bit 2 of Configuration Register 3 (address 07h). ANALOG OUTPUT The ADM1026 has a single analog output from an unsigned 8 bit DAC which produces 0 - 2.5V (independent of the reference voltage setting). The input data for this DAC is contained in the DAC Control register (address 04h) The DAC Control Register defaults to FFh during power-on reset, which produces maximum fan speed. The analog output may be amplified and buffered with external circuitry such as an op-amp and transistor to provide fan speed control. During automatic fan speed control, described later, the four MSBs of this register set the minimum fan speed. Suitable fan drive circuits are given in Figures 11a to 11e. When using any of these circuits, the following points should be noted: 1. All of these circuits will provide an output range from zero to almost +12V, apart from Figure 11a which loses the base-emitter voltage drop of Q1 due to the emitter-follower configuration. 2. To amplify the 2.5V range of the analog output up to 12V, the gain of these circuits needs to be around 4.8. 3. Care must be taken when choosing the op-amp to en- -17- PRELIMINARY TECHNICAL DATA ADM1026 +12V 1 /4 L M 3 2 4 DAC + R2 36k8 R3 3.9k8 R1 100k8 R2 100k8 +1 2 V Q1 2N 22 19A Q3 IR F 9 6 2 0 R1 10k8 DAC Q 1 /Q 2 M B T3 904 DUAL R4 1k8 Figure 11a.Fan Drive Circuit with Op-Amp and Emitter-- Follower +12V Figure 11d. Discrete Fan Drive Circuit with P-Channel MOSFET, SIngle Supply +12V R2 1 0 0 k8 1 /4 L M 3 2 4 DAC - R4 1k 8 Q1 BD136 2S A 9 6 8 Q3 IR F 9 6 2 0 + R3 1k8 R2 39k8 R1 10k8 DAC Q 1 /Q 2 M BT3 904 DUAL R3 3 9 k8 R4 1 0 k8 R1 4 .7 k 8 Figure 11b. Fan Drive Circuit with Op-Amp and PNP Transistor +12V -1 2 V Figure 11e.Discrete Fan Drive Circuit with P-Channel MOSFET, Dual Supply +V 1 /4 L M 3 2 4 DAC + R3 100k8 Q1 IR F 9 6 2 0 +3.3 V 5V or 12 V Fan 10 k typic al R2 39k8 R1 10k8 PW M Q1 N DT305 5L Figure 11f. PWM Fan Drive Circuit using an N-Channel MOSFET Figure 11c. Fan Drive Circuit with Op-Amp and P-Channel MOSFET -18- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 sure that its input common-mode range and output voltage swing are suitable. 4. The op-amp may be powered from the +12V rail alone or from 12V. If it is powered from +12V then the input common-mode range should include ground to accommodate the minimum output voltage of the DAC, and the output voltage should swing below 0.6V to ensure that the transistor can be turned fully off. 5. If the op-amp is powered from -12V then precautions such as a clamp diode to ground may be needed to prevent the base-emitter junction of the output transistor being reverse-biased in the unlikely event that the output of the op-amp should swing negative for any reason. 6. In all these circuits, the output transistor must have an ICMAX greater than the maximum fan current, and be capable of dissipating power due to the voltage dropped across it when the fan is not operating at fullspeed. 7. If the fan motor produces a large back e.m.f when switched off, it may be necessary to add clamp diodes to protect the output transistors in the event that the output goes from full-scale to zero very quickly. PWM OUTPUT In Automatic Fan Speed Control Mode, the four MSBs of the DAC Control Register (address 04h) and PWM Control Register (address 05h) set the minimum values for the DAC and PWM outputs. Note: If both DAC Control and PWM Control is enabled (bits 5, 6 of Configuration Register 1 = 1), the four MSBs of the DAC Control Register (address 04h) define the minimum fan speed values for both the DAC and PWM outputs. The value in the PWM Control Register (address 05h) has no effect. Minimum DAC Code DACMIN = 16 (DAC output voltage = 2.5 D D Code/256) Minimum PWM Duty-Cycle PWMMIN = 6.67 where D is the decimal equivalent of bits 7 to 4 of the register. When the temperature measured by any of the sensors exceeds the corresponding TMIN, the fan is spun up for two seconds with the fan drive set to maximum (full-scale from the DAC or 100% PWM duty-cycle. The fan speed is then set to the minimum as previously defined. As the temperature increases, the fan drive will increase until the temperature reaches TMIN +20oC. The fan drive at any temperature up to 20oC above TMIN is given by: PWM = PWMMIN + (100 - PWMMIN) or DAC = DACMIN + (240 - DACMIN) (TACTUAL - TMIN)/20) For simplicity of the automatic fan speed algorithm, the DAC code increases linearly up to 240, not its full-scale of 255. However, when the temperature exceeds TMIN +20oC, the DAC output will jump to full-scale. S P IN U P FO R 2 S E CO ND S 100% Fan speed may also be controlled using pulse-width modulation (PWM). The PWM output (pin 18) produces a pulsed output with a frequency of approximately 75Hz and a duty-cycle defined by the contents of the PWM Control Register (address 05h). During automatic fan speed control, described below, the four MSBs of this register set the minimum fan speed. The open-drain PWM output must be amplified and buffered to drive the fans. The PWM output is intended to be used with an NMOS driver, but may be inverted by setting bit 1 of Test Register 1(address 14h) if using PMOS drivers. Figure 11f shows how a fan may be driven under PWM control using an N-channel MOSFET. AUTOMATIC FAN SPEED CONTROL (TACTUAL - TMIN)/20) The ADM1026 offers a simple method of controlling fan speed according to temperature without intervention from the host processor. To enable automatic fan speed control, monitoring must be enabled by setting Bit 0 of Configuration Register 1 (address 00h). Automatic fan speed control can be applied to the DAC output, the PWM output, or both, by setting bit 5 and/or 6 of Configuration Register 1. The TMIN registers (addresses 10h to 12h) contain minimum temperature values for the three temperature channels (on-chip sensor and two remote diodes). This is the temperature at which a fan will start to operate when the temperature sensed by the controlling sensor exceeds TMIN. TMIN can be the same or different for all three channels. TMIN is set by writing a two's complement temperature value to the TMIN registers. If any sensor channel is not required for automatic fan speed control, TMIN for that channel should be set to +127oC (01111111). REV. PrP PWM O UT P UT M IN T M IN - 4 o TM IN T E M P E RA T URE T M IN + 20 o Figure 12a. Automatic PWM Fan Control Transfer Function -19- PRELIMINARY TECHNICAL DATA ADM1026 S P IN U P FO R 2 S E CO ND S 255 240 DA C O UT P UT If the fan output has a resistive pullup to +12V (or other voltage greater than 3.3VSTBY) then the fan output can be clamped with a zener diode, as shown in Figure 13b. The zener voltage should be chosen so that it is greater than VIH but less than 3.3VSTBY, allowing for the voltage tolerance of the zener. +1 2 V VCC M IN P ULL UP 4.7k8 T YP . TA C H O OUT PUT F AN (0-7) FA N SP EE D COUNTE R ZD1 * ZE N E R T M IN - 4 o T M IN T E M P E RA T UR E T M IN + 20 o *C HO O S E Z D1 V O L T AG E AP P RO X . 0 .8 x V C C Figure 12b. Automatic DAC Fan Control Transfer Function To ensure that the maximum cooling capacity is always available, the fan drive is always set by the sensor channel demanding the highest fan speed. If the temperature falls, the fan will not turn off until the temperature measured by all three temperature sensors has fallen to their corresponding TMIN - 4oC. This prevents the fan from cycling on and off continuously when the temperature is close to TMIN. Whenever a fan starts or stops during automatic fan speed control, a one-off interrupt is generated at the INT output. This is described in more detail in the section on the ADM1026 Interrupt Structure. FAN INPUTS Figure 13b. Fan with Tach. Pullup to Voltage >VCC e.g. 12V) Clamped with Zener Diode If the fan has a strong pullup (less than 1k ) to +12V, or a totem-pole output, then a series resistor can be added to limit the zener current, as shown in Figure 13c. Alternatively, a resistive attenuator may be used, as shown in Figure 13d. R1 and R2 should be chosen such that: 2V < VPULLUP x R2/(RPULLUP + R1 + R2) < 3.3VSTBY +1 2 V VCC TA C H O O /P P UL L UP T Y P. <1k8 O R T O T E M -P O L E R1 10k8 F AN (0-7) Pins 3 to 6 and 9 to 12 may be configured as fan speed measuring inputs by clearing the corresponding bit(s) of Configuration Register 2 (address 01h) or as general-purpose logic inputs/outputs by setting bits in this register. The power-on default value for this register is 00h, which means all the inputs are set for fan speed measurement. Signal conditioning in the ADM1026 accommodates the slow rise and fall times typical of fan tachometer outputs. The Fan Tach inputs have internal 10k pullup resistors to 3.3VSTBY. In the event that these inputs are supplied from fan outputs which exceed the supply, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figures 13a to 13d show circuits for most common fan tacho outputs. If the fan tacho output is open drain or has a resistive pullup to VCC then it can be connected directly to the fan input, as shown in Figure 13a. +1 2 V VCC FAN SP EE D CO UNT ER ZD1 Z E N E R* *C HO O S E Z D1 V O L T AG E AP P RO X . 0 .8 x V C C Figure 13c. Fan with Strong Tach. Pullup to >VCC or TotemPole Output, Clamped with Zener and Resistor +1 2 V VCC <1k8 R1* TA C H O OUT PUT F AN (0-7) FAN SP EE D CO UNT ER R2* *S E E T E X T Figure 13d. Fan with Strong Tach. Pullup to >VCC or TotemPole Output, Attenuated with R1/R2 FAN SPEED MEASUREMENT P ULL UP 4.7k8 T YP . TA C H O OUT PUT F AN (0-7) FA N SP EE D COUNTER Figure 13a. Fan With Tach Pullup To +VCC. The fan counter does not count the fan tacho output pulses directly, because the fan speed may be less than 1000 RPM and it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 22.5kHz oscillator into the input of an 8-bit counter for two periods of the fan tacho output, as shown in Figure 14, so the accumulated count is actually proportional to the fan tacho period and inversely proportional to the fan speed. -20- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 22.5kHz CLOCK /4 /8 2200 1100 27.27 54.54 1540 770 38.96 77.92 1320 660 45.45 90.9 CONFIG REG. 1 BIT 0 1 FAN0 INPUT 1 FAN1 INPUT FAN0 M EASUREMENT PERIO D FAN1 M EASUREMENT PERIO D 2 3 4 2 3 4 LIMIT VALUES START O F M ONITORING CYCLE Fans generally do not overspeed if run from the correct voltage, so the failure condition of interest is underspeed due to electrical or mechanical failure. For this reason only low-speed limits are programmed into the limit registers for the fans. It should be noted that, since fan period rather than speed is being measured, a fan failure interrupt will occur when the measurement exceeds the limit value. FAN MONITORING CYCLE TIME Figure 14. Fan Speed Measurement The monitoring cycle begins when a one is written to the Monitor Bit (bit 0 of Configuration Register 1). The INT_Enable (Bit 1) should be set to one to enable the INT output. Speed measurement of the Fan 0 channel is initialized on the first rising edge of the fan tach pulse after Start goes low, and oscillator pulses are actually counted from the second rising tach edge to the fourth rising edge. The measurement then switches to Fan 1. Here again, the measurement is initialized on the first tach pulse rising edge after the Fan 0 measurement finishes and oscillator pulses are counted from the second rising edge to the fourth rising edge. This is repeated for the other six fan channels. To accommodate fans of different speed and/or different numbers of output pulses per revolution, a pre-scaler (divisor) of 1, 2, 4 or 8 may be added before the counter. Divisor values for Fans 0 to 3 are contained in the Fan 03 Divisor Register (address 02h) and those for Fans 4 to 7 in the Fan 4-7 Divisor Register (address 03h). The default value is 2, which gives a count of 153 for a fan running at 4400 RPM producing two output pulses per revolution. The count is calculated by the equation: Count = (22.5 x 103x 60) /(RPM x Divisor) For constant speed fans, fan failure is normally considered to have occurred when the speed drops below 70% of nominal, which would correspond to a count of 219. Fullscale (255) would be reached if the fan speed fell to 60% of its nominal value. For temperature-controlled variable speed fans the situation will be different. Table 4 shows the relationship between fan speed and time per revolution at 60%, 70% and 100% of nominal RPM for fan speeds of 1100, 2200, 4400 and 8800 RPM, and the divisor that would be used for each of these fans, based on two tacho pulses per revolution. TABLE 4. FAN SPEEDS AND DIVISORS Divisor Nominal Time per 7 0 % Time per 6 0 % Time per RPM rev RPM rev (70%) RPM rev (60%) (ms) (ms) (ms) The fan speeds are measured in sequence from 0 to 7. The monitoring cycle time depends on the fan speed, the number of tacho output pulses per revolution and the number of fans being monitored. If a fan is stopped or running so slowly that the fan speed counter reaches 255 before the second tach pulse after initialization, or before the fourth tach pulse during measurement, the measurement will be terminated. This will also occur if an input is configured as GPIO instead of fan. Any channels so connected will time out after 255 clock pulses. The worst-case measurement time for a fan-configured channel occurs when the counter reaches 254 from start to the 2nd tach pulse and reaches 255 after the second tach pulse. Taking into account the tolerance of the oscillator frequency, the worst-case measurement time is: 509 where: 509 is the total number of clock pulses. D is the divisor, 1,2, 4 or 8. 0.047 is the worst-case oscillator period in ms. The worst-case fan monitoring cycle time is the sum of the worst case measurement time for each fan. Although the fan monitoring cycle and the analog input monitoring cycle are started together, they are not synchronised in any other way. FAN MANUFACTURERS D 0.047 milliseconds Manufacturers of cooling fans with tachometer outputs are listed below: NMB Tech 9730 Independence Ave. Chatsworth, California 91311 818-341-3355 818-341-8207 /1 /2 REV. PrP 8800 4400 6.82 13.64 6160 3080 9.74 19.48 5280 2640 11.36 22.73 -21- PRELIMINARY TECHNICAL DATA ADM1026 Model 2408NL 2410ML 3108NL 3110KL VCC CI 18 Frame Size 2.36 in sq. X 0.79 in (60mm sq. X 20mm) 2.36 in sq. X 0.98 in (60mm sq. X 25mm) 3.15 in sq. X 0.79 in (80mm sq. X 20mm) 3.15 in sq. X 0.98 in (80mm sq. X 25mm) Airflow CFM RSET 6 7 R1 10k8 Q1 9-16 14-25 25-42 25-40 AD 22 105 TE M P. 1 SE N S O R 3 2 Figure 15. Using the CI Input with a Temperature Sensor GENERAL-PURPOSE I/O PINS Mechatronis Inc. P.O. Box 20 Mercer Island, WA 98040 800-453-4569 Models - Various sizes available with tach output option. Sanyo Denki/Keymarc Electronics 2310 205th, Suite 101 Torrance, CA 90501 310-212-7724 Models - 109P Series CHASSIS INTRUSION INPUT The ADM1026 has 8 pins that are dedicated to generalpurpose logic input/output (pins 1, 2 and 43 to 48), 8 pins that can be configured as general-purpose logic pins or fan speed inputs (pins 3 to 6 and 9 to 12) and one pin that can be configured as GPIO16 or THERM output (pin 42). The GPIO/FAN pins are configured as general-purpose logic pins by setting bits 0 to 7 of Configuration Register 2 (address 01h). Pin 42 is configured as GPIO16 by setting bit 0 of Configuration Register 3, or as THERM output by clearing this bit. Each GPIO pin has four data bits associated with it, two bits in one of the GPIO Configuration Registers (addresses 08h to OBh), one in the GPIO Status Registers (addresses 24h and 25h), and one in the GPIO Mask Registers (addresses 1Ch and 1Dh) Setting a Direction Bit = 1 in one of the GPIO Configuration Registers makes the corresponding GPIO pin an output. Clearing the direction bit to 0 makes it an input. Setting a Polarity Bit = 1 in one of the GPIO Configuration Registers makes the corresponding GPIO pin active high. Clearing the polarity bit to 0 makes it active low. When a GPIO pin is configured as an INPUT, the corresponding bit in one of the GPIO status registers is readonly, and is set when the input is asserted ("asserted" may be high or low depending on the setting of the Polarity Bit). When a GPIO pin is configured as an OUTPUT, the corresponding bit in one of the GPIO status registers becomes read/write. Setting this bit will then assert the GPIO output. (here again, "asserted" may be high or low depending on the setting of the polarity bit). The effect of a GPIO Status Register bit on the INT output can be masked out by setting the corresponding bit in one of the GPIO Mask Registers. When the pin is configured as an output, this bit will automatically be masked to prevent the data written to the status bit from causing an interrupt, with the exception of GPIO16 which must be masked manually by setting bit 7 of Mask Register 4. When configured as inputs, the GPIO pins may be connected to external interrupt sources such as temperature sensors with digital output. Another application of the GPIO pins would be to monitor a processor's Voltage ID code (VID code). The Chassis Intrusion input is an active high input intended for detection and signalling of unauthorised tampering with the system. When this input goes high, the event is latched in bit 6 of Status Register 4 and an interrupt will be generated. The bit will remain set until cleared by writing a zero to it, so long as battery voltage is connected to the VBAT input, even if the ADM1026 is powered off. The CI input will detect chassis intrusion events even when the ADM1026 is powered off (provided battery voltage is applied to VBAT) but will not immediately generate an interrupt. Once a chassis intrusion event has been detected and latched, an interrupt will be generated when the system is powered up. The actual detection of chassis intrusion is performed by an external circuit that will detect (for example), when the cover has been removed. A wide variety of techniques may be used for the detection, for example: - Microswitch that opens or closes when the cover is re moved. - Reed switch operated by magnet fixed to the cover - Hall-effect switch operated by magnet fixed to the cover. - Phototransistor that detects light when cover is removed. The Chassis Intrusion input can also be used for other types of alarm input. Figure 15 shows a temperature alarm circuit using an AD22105 temperature switch sensor. This produces a low-going output when the preset temperature is exceeded, so the output is inverted by Q1 to make it compatible with the CI input. Q1 can be almost any small-signal NPN transistor, or a TTL or CMOS inverter gate may be used if one is available. See the AD22105 data sheet for information on selecting RSET. -22- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 E xt1 T em p E xt 2 T em p 3.3V S T BY 3.3V M AIN +5V V CC P +12V -12V M AS K D AT A FR O M S M BUS (S AM E BIT NA M ES A N D O RD E R AS S T AT U S B IT S ) AIN0 AIN1 0 1 2 3 4 5 6 7 M AS K G AT IN G ! 8 S T AT US RE G IS TE R 1 S T AT US BIT M AS K BIT F RO M A NA LO G /TE M P . V AL UE A ND LIM IT RE G IS TE R S HIG H L I M IT M AS K RE G IS TE R 1 0 1 2 3 4 5 6 7 M AS K G AT IN G ! 8 HI G H A N D L O W L I M IT CO M P A R A T O R S DA T A DE M UL TIP L E XE R 1 = O UT O F L IM IT AIN3 AIN4 AIN5 AIN6 AIN7 M AS K D AT A FR O M S M BUS (S AM E BIT NA M ES A N D O RD E R AS S T AT U S B IT S ) IN T T em p V BA T AIN8 T HE RM AF C RE S E RV E D CI G PIO 16 S T AT US RE G IS TE R 2 AIN2 VA LU E S T AT US BIT IN M AS K BIT O UT L O W L I M IT L AT CH RE S E T M AS K RE G IS TE R 2 0 1 2 3 4 5 6 7 M AS K G AT IN G ! 8 S T AT US RE G IS TE R 4 S T AT US BIT M AS K BIT M AS K D AT A FR O M S M BUS (S AM E BIT NA M ES A N D O RD E R AS S T AT U S B IT S ) F AN 0 M AS K RE G IS TE R 4 CI G PIO 16 0 1 2 3 4 5 6 7 HIG H LIM IT CO M P AR AT O R VA LU E F RO M F A N S P E E D V AL UE A N D L IM IT R EG IST E RS HIG H L I M IT DA T A DE M UL T I P L E X E R F AN 1 F AN 2 F AN 3 F AN 4 F AN 5 F AN 6 F AN 7 M AS K D AT A FR O M S M BUS (S AM E BIT NA M ES A N D O RD E R AS S T AT U S B IT S ) M AS K G AT IN G ! 8 1 = O UT O F L I M IT S T AT US RE G IS TE R 3 S T AT US BIT IN M AS K BIT O UT IN T L AT CH RE S E T M AS K RE G IS TE R 3 IN T E NA BL E M AS K G AT IN G ! 8 G PIO 0 TO GP IO 7 S T AT US R EG IS T ER 5 S T AT US BIT IN T C LE A R M AS KIN G D AT A F RO M S M BU S M AS K R E G IS T E R 5 M AS K BIT M AS K G AT IN G ! 8 G PIO 8 TO G PIO15 S T AT US R EG IS T ER 6 S T AT US BIT M AS KIN G D AT A F RO M S M BU S M AS K R E G IS T E R 6 M AS K BIT Figure 16. ADM1026 Interrupt Structure REV. PrP -23- PRELIMINARY TECHNICAL DATA ADM1026 THE ADM1026 INTERRUPT STRUCTURE The Interrupt Structure of the ADM1026 is shown in Figure 16. Interrupts can come from a number of sources, which are combined to form a common INT output. When INT is asserted, this output pulls low. The INT pin has an internal, 100k pullup resistor. 1. Analog/Temperature Inputs As each analog measurement value is obtained and stored in the appropriate value register, the value and the limits from the corresponding limit registers are fed to the high and low limit comparators. The result of each comparison (1 = out of limit, 0 = in limit) is routed to the corresponding bit input of Interrupt Status Register 1, 2 or 4 via a data demultiplexer, and used to set that bit high or low as appropriate. Status bits are self-clearing. If a bit in a status register is set due to an out-of-limit measurement, it will continue to cause INT to be asserted as long as it remains set, as described below. However, if a subsequent measurement is in limit it will be reset and will not cause INT to be re-asserted. Status bits are unaffected by clearing the interrupt. Interrupt Mask Registers, 1, 2 and 4 have bits corresponding to each of the Interrupt Status Register Bits. Setting an Interrupt Mask Bit high forces the corresponding Status Bit output low, whilst setting an Interrupt Mask Bit low allows the corresponding Status Bit to be asserted. After mask gating, the status bits are all OR'd together to produce the analog and fan interrupt, which is used to set a latch. The output of this latch is OR'd with other interrupt sources to produce the INT output. This will pull low if any unmasked status bit goes high, i.e. when any measured value goes out of limit. When an INT output due to an out-of-limit analog/temp. measurement is cleared by one of the methods described later, the latch is reset. It will not be set again, and INT will not be re-asserted, until the end of the next monitor- ing cycle, even if the status bit remains set or a new analog/temp. event occurs. However, interrupts from other sources such as fan or GPIO can still be asserted. This is illustrated in Figures 17 and 18. Status Register 4 also stores inputs from two other interrupt sources, which operate in a different way from the other status bits. If automatic fan speed control (AFC) is enabled, bit 4 of status register 4 will be set whenever a fan starts or stops. This bit causes a one-off INT output as shown in Figure 19. It is cleared during the next monitoring cycle and if INT has been cleared it will not cause INT to be re-asserted. F AN O N F AN O F F IN T IN T C L E ARE D BY S T A TU S RE G 1 RE AD , B IT 2 O F CO NF IG .RE G . 1 S E T, O R AR A Figure 19. Assertion Of INT Due To AFC Event In a similar way, a change of state at the THERM output (described in more detail later), sets bit 3 of Status Register 4 and causes a one-off INT output. A change of state at the THERM output also causes bit 0 of Status Register 1, bit 1 of Status Register 1, or bit 0 of Status Register 4 to be set, depending on which temperature channel caused the THERM event. This bit will be reset during the next monitoring cycle, provided the temperature channel is within the normal high and low limits. 2. Fan Inputs Fan inputs generate interrupts in a similar way to analog/ temp. inputs, but as the analog/temp. inputs and fan inputs have different monitoring cycles, they have separate inter- ST ART O F ANALO G M O NITO RING CYCLE O UT-OF -LIM IT M EAS URE M ENT LO CAL TE M P. M EAS URE M ENT ST ART O F ANALO G M O NITO RING CYCLE LO CAL TE M P. M EAS URE M ENT ST ART O F ANALO G M O NITO RING CYCLE IN T CLEARE D IN T IN T RE-AS SERT ED Figure 17. Delay After Clearing INT Before Re-assertion S T AR T O F AN AL O G M O N IT O R ING CY C LE O UT -O F -L IM IT M E AS UR E M E N T L O C AL T E M P . M E AS UR E M E N T S T AR T O F AN AL O G M O N IT O R ING CY C LE L O C AL T E M P . M E AS UR E M E N T S T AR T O F AN AL O G M O N IT O R ING CY C LE IN T CL E A RE D IN T CL E A RE D G PIO DE -AS S E RT E D IN T NE W IN T F RO M F AN NE W IN T F RO M G PIO IN T R E-A SS E R TE D Figure 18. Other Interrupt Sources Can Re-assert INT Immediately -24- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 rupt circuits. As the speed of each fan is measured, the output of the fan speed counter is stored in a value register. The result is compared to the fan speed limit and used to set or clear a bit in Status Register 3. In this case the fan is only monitored for under-speed (fan counter > fan speed limit). Mask Register 3 is used to mask fan interrupts. After mask gating, the fan status bits are OR'd together and used to set a latch, whose output is OR'd with other interrupt sources to produce the INT output. Like the analog/temp. interrupt, an INT output caused by an out-of-limit fan speed measurement, once cleared, will not be re-asserted until the end of the next monitoring cycle, although other interrupt sources may cause INT to be asserted. 3. GPIO and CI Pins When GPIO pins are configured as inputs, asserting a GPIO input (high or low, depending on polarity) sets the corresponding GPIO status bit in Status Registers 5 and 6 or bit 7 of Status Register 4 (GPIO16). A chassis intrusion event sets bit 6 of Status Register 4. The GPIO and CI status bits, after mask gating, are OR'd together and OR'd with other interrupt sources to produce the INT output. GPIO and CI interrupts are not latched and cannot be cleared by normal interrupt clearing. They can only be cleared by masking the status bits or by removing the source of the interrupt. ENABLING AND CLEARING INTERRUPTS T HE RM L IM IT T HE RM L IM IT -5 o C the temperature is close to the limit, a fixed hysteresis of 5oC is provided. THERM will only be de-asserted when the measured temperature of all three sensors is 5oC below the limit. Whenever the THERM output changes, INT will be asserted, as shown in Figure 20. However, this is edge-triggered, so if INT is subsequently cleared by one of the methods previously described, it will not be re-asserted, even if THERM remains asserted. THERM will only cause INT to be asserted again when it changes state. Note that the THERM pin is bidirectional, so THERM may be pulled low externally as an input. This will cause the PWM and DAC outputs to go to full-scale until THERM is returned high again. T E M P E RA T UR E THERM IN T IN T C LE A RE D BY S T AT US R EG 1 RE AD , B IT 2 O F C O N F IG .RE G . 1 S ET , O R A RA Figure 20. Assertion Of INT Due To THERM Event RESET INPUT AND OUTPUTS The INT output is enabled when Bit 1 of Configuration Register 1 (INT_Enable) is high, and Bit 2 (INT_Clear) is low. INT may be cleared if: Status Register 1 is read. Ideally, if polling the Status Registers trying to identify interrupt sources, Status Register 1 should be polled last, since a read of Status Register 1 clears all the other Interrupt Status Registers. the ADM1026 receives the Alert Response Address (0001 100) over the SMBus. bit 2 of Configuration Register 1 is set. PIN The ADM1026 has two active-low, power-on reset outputs, RESETMAIN and RESETSTBY. These operate as follows: RESETSTBY monitors 3.3V STBY. At power-up RESETSTBY will be asserted (pulled low) until 180ms after 3.3VSTBY rises above the reset threshold. RESETMAIN monitors 3.3V MAIN. At power-up RESETMAIN will be asserted (pulled low) until 180ms after 3.3V MAIN rises above the reset threshold. If 3.3V MAIN rises with or before DVCC, RESETMAIN will remain asserted until 180ms after RESETSTBY is negated. RESETMAIN can also function as a RESET input. Pulling this pin low will reset the system to power-on defaults. 3.3V S TB Y ~1V - BIDIRECTIONAL THERM The ADM1026 has a second interrupt pin (GPIO16/THERM, pin 42) that responds only to thermal events, e.g. if any of the three temperature sensors exceeds its THERM temperature limit. This output is enabled by setting bit 4 of Configuration Register 1 (Reg.00h). Three thermal limit registers are provided for the three temperature sensors at addresses 0Dh to 0Fh. These registers are dedicated to the THERM output and none of the other limit registers have any effect on the THERM output. If any of the temperature inputs exceeds the corresponding limit, THERM will be asserted (low) and the DAC and PWM outputs will go to maximum to drive any cooling fans to full speed. To avoid cooling fans cycling on and off continually when REV. PrP 3.3V M AIN ~1V R E S ET ST B Y R E S ET M A IN 180m s 180m s P O W ER -O N R ES E T Figure 21. Operation Of Reset Outputs NAND TREE TESTS A NAND tree is provided in the ADM1026 for Auto-25- PRELIMINARY TECHNICAL DATA ADM1026 mated Test Equipment (ATE) board level connectivity testing. This allows the functionality of all digital inputs to be tested in a simple manner and any pins that are nonfunctional or shorted together to be identified. The structure of the NAND tree is shown in Figure 22. The device is placed into NAND Tree Test Mode by powering up with pin 25 held high. This pin is sampled automatically after power-up and if it is connected high, then the NAND test mode is invoked. G P IO 8 G P IO 9 FAN0 G P IO 1 0 FAN1 G P IO 1 1 FAN2 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 FAN0 FAN1 FAN2 FAN3 IN T FAN3 CI FAN4 G P IO 1 2 FAN4 FAN5 FAN6 G P IO 1 3 SDA FAN5 SCL FAN6 G P IO 1 4 FAN7 G P IO 1 5 SCL SDA FAN7 G P IO 1 6 NTESTO UT CI INT Figure 22. NAND Tree The NAND tree test may be carried out in one of two ways. NTESTOUT 1. Start with all inputs low and take them high in turn, starting with the input nearest to NTEST_OUT (GPIO16/THERM) and working back up the tree to the input furthest from NTESTOUT (INT). This should give the characteristic output pattern shown in Figure 23, with NTESTOUT toggling each time an input is taken high. Figure 23. NAND Tree Test Taking Inputs High In Turn 1. Start with all inputs high and take them low in turn, starting with the input furthest from NTEST_OUT (INT) and working down the tree to the input nearest to NTEST_OUT (GPIO16/THERM). This should give a similar output pattern to Figure 24. Notes: 1. When generating test waveforms, a typical propagation delay of 500 ns through the NAND tree should be allowed for. 2. If any of the inputs shown in Figure 22 are unused, they should not be connected direct to ground, but via a resistor such as 10k . This will allow the ATE (Automatic Test Equipment) to drive every input high so that the NAND tree test can be properly carried out. -26- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 G PIO 16 G PIO 15 G PIO 14 IN T CI S DA S CL F AN7 F AN6 F AN5 F AN4 F AN3 F AN2 F AN1 G PIO 13 G PIO 12 G PIO 11 G PIO 10 G PIO 9 G PIO 8 F AN 0 F AN 1 NT E S T O U T Figure 25. NAND Tree Test With GPIO11 Stuck Low Figure 25 shows the effect of one input being stuck low. F AN0 G P IO 8 G P IO 9 G P IO 10 G P IO 11 G P IO 12 G P IO 13 G P IO 14 G P IO 15 G P IO 16 NT E ST O U T The output pattern is normal until the stuck input is reached. Because that input is permanently low, neither it nor any inputs further up the tree can have any effect on the output. G PIO 16 G PIO 15 G PIO 14 G PIO 13 G PIO 12 G PIO 11 G PIO 10 G PIO 9 G PIO 8 F AN 0 F AN 1 NT E S T O U T Figure 24. NAND Tree Test taking Inputs Low In Turn In the event of an input being non-functional(stuck high or low) or two inputs shorted together, the output pattern will be different. Some examples are given in Figures 25 to 27. Figure 26. NAND Tree Test With One Input Stuck High Figure 26 shows the effect of one input being stuck high. Taking GPIO12 high should take the output high. However, the next input up the tree, GPIO11, is already high, so the output immediately goes low again, causing a missing pulse in the output pattern. REV. PrP -27- PRELIMINARY TECHNICAL DATA ADM1026 G PIO 16 G PIO 15 G PIO 14 G PIO 13 G PIO 12 G PIO 11 G PIO 10 G PIO 9 G PIO 8 F AN 0 F AN 1 NT E S TO UT mode. Setting Bit 0 high starts the monitoring loop. Bit 1 enables or disables the INT Interrupt output. Setting Bit 1 high enables the INT output, setting bit 1 low disables the output. Bit 2 is used to clear the INT interrupt output when set high. GPIO pins and Interrupt Status register contents will not be affected. Bit 3 configures pins 27 and 28 as the second external temperature channel when 0, and as AIN8 and AIN9 when set to 1. Bit 4 enables the THERM output when set to 1. Bit 5 enables automatic fan speed control on the DAC output when set to 1. Bit 6 enables automatic fan speed control on the PWM output when set to 1. Bit 7 performs a soft reset when set to 1. Configuration Register 3 Bit 0 configures pin 42 as GPIO when set to 1 or as THERM when cleared to 0. Bit 1 clears the CI latch when set to 1. A 0 must be written thereafter to allow subsequent CI detection. Bit 2 selects VREF as 2.5V when set to 1 or as 1.82V when cleared to 0. Bits 3 to 5 are unused. Bits 6 and 7 set up GPIO16 for direction and polarity. STARTING CONVERSION Figure 27. NAND Tree Test With Two Inputs Shorted A similar effect occurs if two adjacent inputs are shorted together. The example in Figure 27 assumes that the current sink capability of the circuit driving the inputs is considerably higher than the source capability, so the inputs will be low if either is low, but high only if both are high. When GPIO12 goes high the output should go high, but since GPIO12 and GPIO11 are shorted, they both go high together, causing a missing pulse in the output pattern. USING THE ADM1026 When power is first applied, the ADM1026 performs a power-on reset on all its registers (not EEPROM), which sets them to default conditions as shown in Table 6. In particular it should be noted that all GPIO pins are configured as inputs to avoid possible conflicts with circuits trying to drive these pins. The ADM1026 can also be initialized at any time by writing a 1 to Bit 7 of Configuration Register 1, which sets some registers to their default power-on conditions. This Bit should be cleared by writing a 0 to it. After power-up, the ADM1026 must be configured to the user's specific requirements. This consists of: writing values to the limit registers. configuring pins 3 to 6 and 9 to 12 as fan inputs or GPIO, using Configuration Register 2 (address 01h) setting the fan divisors using the Fan Divisor Registers (addresses 02h and 03h). configuring the GPIO pins for input/output, polarity, using GPIO Configuration Registers 1 to 4 (addresses 08h to 0Bh) and bits 6 and 7 of Configuration Register 3. setting mask bits in Mask Registers 1 to 6 (addresses 18h to 1Dh) for any inputs that are to be masked out. setting up Configuration Registers 1 and 3, as follows: The monitoring function (Analog inputs, temperature, and fan speeds) in the ADM1026 is started by writing to Configuration Register 1 and setting Start (Bit 0), high. The INT_Enable (Bit 1) should be set to 1, and INT Clear (Bit 2) set to 0 to enable interrupts. The THERM enable bit (bit 4) should be set to 1 to enable temperature interrupts at the THERM pin. Apart from initially starting together, the analog measurements and fan speed measurements proceed independently, and are not synchronised in any way. REDUCED POWER AND SHUTDOWN MODE - Configuration Register 1 Bit 0 controls the monitoring loop of the ADM1026. Setting Bit 0 low stops the monitoring loop and puts the ADM1026 into a low power mode thereby reducing power consumption. Serial bus communication is still possible with any register in the ADM1026 while in low-power The ADM1026 can be placed in a low-power mode by setting bit 0 of the Configuration register to 0. This disables the internal ADC. Full shutdown mode may then be achieved by setting bit 7 of the Test Register 1 (address 14h) to 1. This turns off the analog output and stops the monitoring cycle, if running, but it does not affect the condition of any of the registers. The device will return to its previous state when this bit is reset to zero. However, it should be noted that if the device is placed into Shutdown Mode and woken up again, RSTMAIN and RSTSTBY will both assert low. Care must be taken since if either of these pins connect to the CPU then this can cause an entire system reset. In the Shutdown Mode, the ADM1026 current consumption is reduced to 250A typical. -28- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 SOFTWARE RESET FUNCTION As previously mentioned, the ADM1026 can be reset in software by setting bit 7 of Configuration Register 1 (Reg. 00h) = 1. This bit should then be cleared to 0. Note that the software reset differs from a power-on reset in that only some of the ADM1026 registers get re-initialized to their power-on default values. The registers that are initialized to their default values by the Software Reset are: - Configuration Registers (Registers 00h to 0Bh) - Mask Registers 1 to 6, Internal Temp Offset, and Status Registers 4, 5 and 6 (Registers 18h to 25h) - All value registers (Registers 1Fh, 20h to 3Fh) - External 1 and External 2 Offset Registers (6Eh, 6Fh) Note that the Limit Registers (0Dh to 12h, 40h to 6Dh) are not reset by the Software Reset function. This can be useful if you need to reset the part but do not want to have to reprogram all parameters again. Note that a Power-on Reset initializes all registers on the ADM1026 including the Limit Registers. REV. PrP -29- PRELIMINARY TECHNICAL DATA ADM1026 ADM1026 REGISTERS TABLE 5. ADDRESS POINTER REGISTER Bit 7-0 Name Address Pointer R/W Write Description Address of ADM1026 Registers. See the tables below for detail. TABLE 6. LIST OF REGISTERS Hex Address 00 01 02 03 04 Name Configuration 1 Configuration 2 Fan 0-3 Divisor Fan 4-7 Divisor DAC Control Power on Value (Hex or Binary Bit 7 - 0) 00h 00h 55h 55h FFh Description Configures various operating parameters Configures pins 3-6 and 9-12 as fan inputs or GPIO Sets oscillator frequency for Fan 0 - 3 speed measurement Sets oscillator frequency for Fan 4 - 7 speed measurement Contains value for fan speed DAC (analog fan speed control) or minimum value for automatic fan speed control Contains value for PWM fan speed control or minimum value for automatic fan speed control For factory use only. Config. register for THERM, VREF and GPIO16 Configures GPIO0 to GPIO3 as input or output and as active high or active low Configures GPIO4 to GPIO7 as input or output and as active high or active low Configures GPIO8 to GPIO11 as input or output and as active high or active low Configures GPIO12 to GPIO15 as input or output and as active high or active low For factory use only 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 PWM Control EEPROM Register 1 Configuration Register 3 GPIO Config 1 GPIO Config 2 GPIO Config 3 GPIO Config 4 EEPROM Register 2 Int Temp THERM Limit TDM1 THERM Limit TDM2 THERM Limit Int Temp TMIN TDM1 TMIN TDM2 TMIN EEPROM Register 3 Test Register 1 FFh 00h 00h 00h 00h 00h 00h 00h 37h (55 C) 50h (80oC) 50h (80oC) 28h (40oC) 40h (64oC) 40h (64oC) 00h 00h -30- o High limit for THERM interrupt output based on internal temperature measurement High limit for THERM interrupt output based on remote channel 1 (D1) temperature measurement High limit for THERM interrupt output based on remote channel 2 (D2) temperature measurement TMIN value for automatic fan speed control based on internal temperature measurement TMIN value for automatic fan speed control based on remote channel 1 (D1) temperature measurement TMIN value for automatic fan speed control based on remote channel 2 (D2) temperature measurement Configures EEPROM for read/write/erase etc. Manufacturer's Test Register REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 Hex Address 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 REV. PrP Name Test Register 2 Manufacturer's ID Revision Mask Register 1 Mask Register 2 Mask Register 3 Mask Register 4 Mask Register 5 Mask Register 6 Int Temp Offset Int Temp Value Status Register 1 Status Register 2 Status Register 3 Status Register 4 Status Register 5 Status Register 6 VBAT Value AIN8 Value TDM1 Value TDM2/A IN9 Value 3.3VSTBY Value 3.3VMAIN Value +5V Value VCCP Value +12V Value -12V Value AIN0 Value AIN1 Value AIN2 Value AIN3 Value AIN4 Value Power on Value (Hex or Binary Bit 7 - 0) 00h 41h 4xh 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h -31- Description For manufacturer's use only Contains manufacturer's ID code Contains code for major and minor revisions Interrupt Mask register for temperature and supply voltage faults Interrupt mask register for analog input faults Interrupt mask register for fan faults Interrupt mask register for local temp, VBAT, AIN8, THERM, AFC, CI and GPIO16 Interrupt mask register for GPIO0 to GPIO7 Interrupt mask register for GPIO8 to GPIO15 Offset register for internal temperature measurement Measured temperature from on-chip sensor Interrupt status register for external temp and supply voltage faults Interrupt status register for analog input faults Interrupt status register for fan faults Interrupt status register for local temp, VBAT, AIN8, THERM, AFC, CI and GPIO16 Interrupt status register for GPIO0 to GPIO7 Interrupt status register for GPIO8 to GPIO15 Measured value of VBAT Measured value of AIN8 Measured value of remote temperature channel 1 (D1) Measured value of remote temperature channel 2 (D2) or AIN9 Measured value of standby digital VCC Measured value of 3.3VMAIN Measured value of +5V supply Measured value of processor core voltage Measured value of +12V supply Measured value of -12V supply Measured value of AIN0 Measured value of AIN1 Measured value of AIN2 Measured value of AIN3 Measured value of AIN4 PRELIMINARY TECHNICAL DATA ADM1026 Hex Address 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 Name AIN5 Value AIN6 Value AIN7 Value FAN0 Value FAN1 Value FAN2 Value FAN3 Value FAN4 Value FAN5 Value FAN6 Value FAN7 Value TDM1 High Limit TDM2/AIN9 High Limit 3.3VSTBY High Limit 3.3VMAIN High Limit +5V High Limit VCCP High Limit +12V High Limit -12V High Limit TDM1 Low Limit TDM2/AIN9 Low Limit 3.3VSTBY Low Limit 3.3VMAIN Low Limit +5V Low Limit VCCP Low Limit +12V Low Limit -12V Low Limit AIN0 High Limit AIN1 High Limit AIN2 High Limit AIN3 High Limit Power on Value (Hex or Binary Bit 7 - 0) 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 64h (100 C) 64h (100oC) FFh FFh FFh FFh FFh FFh 80h 80h 00h 00h 00h 00h 00h 00h FFh FFh FFh FFh o Description Measured value of AIN5 Measured value of AIN6 Measured value of AIN7 Measured speed of Fan 0 Measured speed of Fan 1 Measured speed of Fan 2 Measured speed of Fan 3 Measured speed of Fan 4 Measured speed of Fan 5 Measured speed of Fan 6 Measured speed of Fan 7 High limit for remote temperature channel 1 (D1) measurement High limit for remote temperature channel 2 (D2) or AIN 9 measurement High limit for digital VCC measurement High limit for analog VCC measurement High limit for +5V supply measurement High limit for processor core voltage measurement High limit for +12V supply measurement High limit for -12V supply measurement Low limit for remote temperature channel 1 (D1) measurement Low limit for remote temperature channel 2 (D2) or AIN 9 measurement Low limit for digital VCC measurement Low limit for analog VCC measurement Low limit for +5V supply Low limit for processor core voltage measurement Low limit for +12V supply measurement Low limit for -12V supply measurement High limit for AIN0 measurement High limit for AIN1 measurement High limit for AIN2 measurement High limit for AIN3 measurement -32- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 Hex Address 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F Name AIN4 High Limit AIN5 High Limit AIN6 High Limit AIN7 High Limit AIN0 Low Limit AIN1 Low Limit AIN2 Low Limit AIN3 Low Limit AIN4 Low Limit AIN5 Low Limit AIN6 Low Limit AIN7 Low Limit FAN0 High Limit FAN1 High Limit FAN2 High Limit FAN3 High Limit FAN4 High Limit FAN5 High Limit FAN6 High Limit FAN7 High Limit Int. Temp. High Limit Int. Temp. Low Limit VBAT High Limit VBAT Low Limit AIN8 High Limit AIN8 Low Limit Ext1 Temp Offset Ext2 Temp Offset Power on Value (Hex or Binary Bit 7 - 0) FFh FFh FFh FFh 00h 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 50h (80oC) 80h FFh 00h FFh 00h 00h 00h Description High limit for AIN4 measurement High limit for AIN5 measurement High limit for AIN6 measurement High limit for AIN7 measurement Low limit for AIN0 measurement Low limit for AIN1 measurement Low limit for AIN2 measurement Low limit for AIN3 measurement Low limit for AIN4 measurement Low limit for AIN5 measurement Low limit for AIN6 measurement Low limit for AIN7 measurement High limit for Fan 0 speed measurement (no low limit) High limit for Fan 1 speed measurement (no low limit) High limit for Fan 2 speed measurement (no low limit) High limit for Fan 3 speed measurement (no low limit) High limit for Fan 4 speed measurement (no low limit) High limit for Fan 5 speed measurement (no low limit) High limit for Fan 6 speed measurement (no low limit) High limit for Fan 7 speed measurement (no low limit) High limit for local temperature measurement Low limit for local temperature measurement High limit for VBAT measurement Low limit for VBAT measurement High limit for AIN8 measurement Low limit for AIN8 measurement Offset register for remote temperature channel 1 Offset register for remote temperature channel 2 REV. PrP -33- PRELIMINARY TECHNICAL DATA ADM1026 DETAILED REGISTER DESCRIPTIONS TABLE 7. REGISTER 00H, CONFIGURATION REGISTER 1(POWER-ON DEFAULT 00H) Bit 0 1 2 Name Monitor = 0 Int Enable = 0 Int Clear = 0 R/W R/W R/W R/W Description When this bit is set the ADM1026 monitors all voltage, temperature and fan channels in a round robin manner. When this bit is set the INT output pin is enabled. Setting this bit will clear an interrupt from the voltage, temperature or fan speed channels. Because GPIO interrupts are level triggered, this bit will have no effect on interrupts originating from GPIO channels. This bit is cleared by writing a 0 to it. If in monitoring mode voltages, temperatures and fan speeds will continue to be monitored after writing to this bit to clear an interrupt, so an interrupt may be set again on the next monitoring cycle. When this bit is 1 the ADM1026 monitors voltage (AIN8 and AIN9) on pins 28 and 27 respectively. When this bit is 0, the ADM1026 monitors a second thermal diode temperature channel, D2, on these pins. If the second thermal diode channel is not being used, it is recommended that bit be set to 1. When this bit is 1 the THERM pin (Pin 42) will be asserted (go low) if any of the THERM limits are exceeded. If THERM is pulled low as an input, the DAC and PWM outputs are forced to full-scale until THERM is taken high. When this bit is 1 the DAC output is enabled for automatic fan speed control (AFC) based on temperature. When this bit is 0 the DAC Output reflects the value in Reg 04h, DAC Control Register. When this bit is 1 the PWM output is enabled for automatic fan speed control (AFC) based on temperature. When this bit is 0 the PWM Output reflects the value in Reg 05h, PWM Control Register. Writing a 1 to this bit restores all registers to the power on defaults. This bit is cleared by writing a 0 to it. For more info, see S/W Reset section. 3 Enable Voltage / Ext2 = 0 R/W 4 Enable THERM = 0 R/W 5 Enable DAC AFC = 0 R/W 6 Enable PWM AFC = 0 R/W 7 Software Reset = 0 R/W TABLE 8. REGISTER 01H, CONFIGURATION REGISTER 2 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name R/W Description When this bit is 1, pin 3 is enabled as a General Purpose IO pin (GPIO0), otherwise it is a Fan Tach measurement input (Fan 0). When this bit is 1, pin 4 is enabled as a General Purpose IO pin (GPIO1), otherwise it is a Fan Tach measurement input (Fan 1). When this bit is 1, pin 5 is enabled as a General Purpose IO pin (GPIO2), otherwise it is a Fan Tach measurement input (Fan 2). When this bit is 1, pin 6 is enabled as a General Purpose IO pin (GPIO3), otherwise it is a Fan Tach measurement input (Fan 3). When this bit is 1, pin 9 is enabled as a General Purpose IO pin (GPIO4), otherwise it is a Fan Tach measurement input (Fan 4). When this bit is 1, pin 10 is enabled as a General Purpose IO pin (GPIO5), otherwise it is a Fan Tach measurement input (Fan 5). When this bit is 1, pin 11 is enabled as a General Purpose IO pin (GPIO6), otherwise it is a Fan Tach measurement input (Fan 6). When this bit is 1, pin 12 is enabled as a General Purpose IO pin (GPIO7), otherwise it is a Fan Tach measurement input (Fan 7). Enable GPIO0 / Fan0 = 0 R/W Enable GPIO1 / Fan1 = 0 R/W Enable GPIO2 / Fan2 = 0 R/W Enable GPIO3 / Fan3 = 0 R/W Enable GPIO4 / Fan4 = 0 R/W Enable GPIO5 / Fan5 = 0 R/W Enable GPIO6 / Fan6 = 0 R/W Enable GPIO7 / Fan7 = 0 R/W -34- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 9. REGISTER 02H, FANS 0 TO 3 FAN DIVISOR REGISTER (POWER-ON DEFAULT 55H) Bit 1-0 Name Fan 0 Divisor R/W R/W Description Sets the oscillator prescaler division ratio for Fan 0 speed measurement. The division ratios, oscillator frequencies and typical fan speeds (based on 2 tach pulses per rev.) are as follows: Code Divide-by Osc. Frequency (kHz) Fan Speed (RPM) 00 1 22.5 8800, nominal, for count of 153 01 2 11.25 4400 , nominal, for count of 153 10 4 5.62 2200 , nominal, for count of 153 11 8 2.81 1100 , nominal, for count of 153 Same as for Fan 0 Same as for Fan 0 Same as for Fan 0 3-2 5-4 7-6 Fan 1 Divisor Fan 2 Divisor Fan 3 Divisor R/W R/W R/W TABLE 10. REGISTER 03H, FANS 4 TO 7 FAN DIVISOR REGISTER (POWER-ON DEFAULT 55H) Bit 1-0 Name Fan 4 Divisor R/W R/W Description Sets the oscillator prescaler division ratio for Fan 4 speed measurement. The division ratios, oscillator frequencies and typical fan speeds (based on 2 tach pulses per rev.) are as follows: Code Divide-by Osc. Frequency (kHz) Fan Speed (RPM) 00 1 22.5 8800, nominal, for count of 153 01 2 11.25 4400 , nominal, for count of 153 10 4 5.62 2200 , nominal, for count of 153 11 8 2.81 1100 , nominal, for count of 153 Same as for Fan 4 Same as for Fan 4 Same as for Fan 4 3-2 5-4 7-6 Fan 5 Divisor Fan 6 Divisor Fan 7 Divisor R/W R/W R/W TABLE 11. REGISTER 04H, DAC CONTROL REGISTER (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the value to which the Fan Speed DAC is programmed in normal mode, or the 4 MSBs contain the Min Fan Speed in Auto Fan Speed control mode. 7-0 DAC Control TABLE 12. REGISTER 05H, PWM CONTROL REGISTER (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the value to which the PWM Fan Speed is programmed in normal mode, or the 4 MSBs contain the Min Fan Speed in Auto Fan Speed control mode. 0000 = 0% Duty Cycle 0001 = 7% Duty Cycle | | 0101 = 33% Duty Cycle 0110 = 40% Duty Cycle 0111 = 47% Duty Cycle | | 1110 = 93% Duty Cycle 1111 = 100% Duty Cycle Undefined. -35- 7-4 PWM Control 3-0 Unused R REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 13. REGISTER 06H, EEPROM REGISTER 1 (POWER-ON DEFAULT 00H) Bit 7-0 Name Factory Use R/W R Description For factory use only. Do NOT write to this register. TABLE 14. REGISTER 07H, CONFIGURATION REGISTER 3 (POWER-ON DEFAULT 00H) Bit 0 1 2 5-3 6 7 Name Enable GPIO16/ THERM = 0 CI Clear = 0 VREF Select = 0 Unused GPIO16 Direction GPIO16 Polarity R/W R/W R/W R/W R R/W R/W Description When this bit is 1, pin 42 is enabled as a General Purpose IO pin (GPIO16), otherwise it is the THERM output. Writing a 1 to this bit will clear the CI latch. This bit is cleared by writing a 0 to it. When this bit is 0, VREF (pin 24) outputs 1.82V, otherwise it outputs 2.5V. Undefined, will read back 0. When this bit is 0, GPIO16 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO16 is active low, otherwise it is active high. TABLE 15. REGISTER 08H, GPIO CONFIGURATION REGISTER 1 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name GPIO0 Direction GPIO0 Polarity GPIO1 Direction GPIO1 Polarity GPIO2 Direction GPIO2 Polarity GPIO3 Direction GPIO3 Polarity R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is 0, GPIO0 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO0 is active low, otherwise it is active high. When this bit is 0, GPIO1 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO1 is active low, otherwise it is active high. When this bit is 0, GPIO2 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO2 is active low, otherwise it is active high. When this bit is 0, GPIO3 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO3 is active low, otherwise it is active high. TABLE 16. REGISTER 09H, GPIO CONFIGURATION REGISTER 2 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name GPIO4 Direction GPIO4 Polarity GPIO5 Direction GPIO5 Polarity GPIO6 Direction GPIO6 Polarity GPIO7 Direction GPIO7 Polarity R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is 0, GPIO4 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO4 is active low, otherwise it is active high. When this bit is 0, GPIO5 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO5 is active low, otherwise it is active high. When this bit is 0, GPIO6 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO6 is active low, otherwise it is active high. When this bit is 0, GPIO7 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO7 is active low, otherwise it is active high. -36REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 17. REGISTER 0AH, GPIO CONFIGURATION REGISTER 3 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name GPIO8 Direction GPIO8 Polarity GPIO9 Direction GPIO9 Polarity GPIO10 Direction GPIO10 Polarity GPIO11 Direction GPIO11 Polarity R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is 0, GPIO8 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO8 is active low, otherwise it is active high. When this bit is 0, GPIO9 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO9 is active low, otherwise it is active high. When this bit is 0, GPIO10 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO10 is active low, otherwise it is active high. When this bit is 0, GPIO11 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO11 is active low, otherwise it is active high. TABLE 18. REGISTER 0BH, GPIO CONFIGURATION REGISTER 4 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name GPIO12 Direction GPIO12 Polarity GPIO13 Direction GPIO13 Polarity GPIO14 Direction GPIO14 Polarity GPIO15 Direction GPIO15 Polarity R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is 0, GPIO12 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO12 is active low, otherwise it is active high. When this bit is 0, GPIO13 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO13 is active low, otherwise it is active high. When this bit is 0, GPIO14 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO14 is active low, otherwise it is active high. When this bit is 0, GPIO15 is configured as an input, otherwise, it is an output. When this bit is 0, GPIO15 is active low, otherwise it is active high. TABLE 19. REGISTER 0CH, EEPROM REGISTER 2 (POWER-ON DEFAULT 00H) Bit 7-0 Name Factory Use R/W R Description For factory use only. Do NOT write to this register. TABLE 20. REGISTER 0DH, INTERNAL TEMPERATURE THERM LIMIT (POWER-ON DEFAULT 37H (55OC)) Bit 7-0 Name Int Temp THERM Limit R/W R/W Description This register contains the THERM limit for the Internal Temperature Channel. Exceeding this limit will cause the THERM output pin to be asserted. TABLE 21. REGISTER 0EH, TDM1 THERM LIMIT (POWER-ON DEFAULT 50H (80OC)) Bit 7-0 Name TDM1 THERM Limit R/W R/W Description This register contains the THERM limit for the TDM1 Temperature Channel. Exceeding this limit will cause the THERM output pin to be asserted. -37- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 22. REGISTER 0FH, TDM2 THERM LIMIT (POWER-ON DEFAULT 50H (80OC)) Bit 7-0 Name TDM2 THERM Limit R/W R/W Description This register contains the THERM limit for the TDM2 Temperature Channel. Exceeding this limit will cause the THERM output pin to be asserted. TABLE 23. REGISTER 10H, INTERNAL TEMPERATURE TMIN (POWER-ON DEFAULT 28H (40OC)) Bit 7-0 Name Internal Temp TMIN R/W R/W Description This register contains the TMIN value for automatic fan speed control based on the Internal Temperature Channel. TABLE 24. REGISTER 11H, TDM1 TEMPERATURE TMIN (POWER-ON DEFAULT 40H (64OC)) Bit 7-0 Name TDM1 Temp TMIN R/W R/W Description This register contains the TMIN value for automatic fan speed control based on the TDM1 Temperature Channel. TABLE 25. REGISTER 12H, TDM2 TEMPERATURE TMIN (POWER-ON DEFAULT 40H (64OC)) Bit Name R/W R/W Description This register contains the TMIN value for automatic fan speed control based on the TDM2 Temperature Channel. 7-0 TDM2 Temp TMIN TABLE 19. REGISTER 13H, EEPROM REGISTER 3 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name Read Write Erase Write Protect Test Mode bit 0 Test Mode bit 1 Test Mode bit 2 Clock Extend R/W R/W R/W R/W Description Setting this bit puts the EEPROM into Read mode. Setting this bit puts the EEPROM in Write (program) mode. Setting this bit puts the EEPROM into Erase mode. Read/Write Setting this bit protects the EEPROM against accidental writing or erasure. Once This bit is write-once and can only be cleared by power-on reset. R/W R/W R/W R/W Test mode bit. For factory use only. Test mode bit. For factory use only. Test mode bit. For factory use only. Setting this bit enables SMBus clock extension. The ADM1026 can pull SCL low to extend the clock pulse if it cannot acccept any more data. It is recommended to set this bit to 1 to extend the clock pulse during repeated EEPROM write or block write operations. TABLE 27. REGISTER 14H, MANUFACTURER'S TEST REGISTER 1 (POWER-ON DEFAULT 00H) Bit 7-0 Name Manufacturer's Test 1 R/W R/W Description This register is used by the manufacturer for test purposes. It should not be read from or written to in normal operation. TABLE 28. REGISTER 15H, MANUFACTURER'S TEST REGISTER 2 (POWER-ON DEFAULT 00H) Bit 7-0 Name Manufacturer's Test 2 R/W R/W Description This register is used by the manufacturer for test purposes. It should not be read from or written to in normal operation. -38- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 29. REGISTER 16H, MANUFACTURER'S ID (POWER-ON DEFAULT 41H) Bit 7-0 Name Manufacturer's ID Code R/W R Description This register contains the manufacturer's ID code. TABLE 30. REGISTER 17H, REVISION REGISTER (POWER-ON DEFAULT 4xH) Bit Name R/W R R Description This nibble contains the manufacturer's code for minor revisions to the device. Rev 1 = 0h, Rev 2 = 1h, etc. This nibble denotes the generation of the device. For the ADM1026 this nibble will read 4h. 3-0 Minor Revision Code 7-4 Major Revision Code TABLE 31. REGISTER 18H, MASK REGISTER 1 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name Ext1 Temp Mask = 0 Ext 2 Temp /AIN9 Mask = 0 3.3VSTBY Mask = 0 3.3VMAIN Mask = 0 +5V Mask = 0 VCCP Mask = 0 +12V Mask = 0 -12V Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set, interrupts generated on the Ext1 Temp channel are masked out. When this bit is set, interrupts generated on the Ext2 / AIN9 channel are masked out. When this bit is set, interrupts generated on the 3.3VSTBY Voltage channel are masked out. When this bit is set, interrupts generated on the 3.3VMAIN Voltage channel are masked out. When this bit is set, interrupts generated on the +5V Voltage channel are masked out. When this bit is set, interrupts generated on the VCCP Voltage channel are masked out. When this bit is set, interrupts generated on the +12V Voltage channel are masked out. When this bit is set, interrupts generated on the -12V Voltage channel are masked out. TABLE 32. REGISTER 19H, MASK REGISTER 2 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name AIN0 Mask = 0 AIN1 Mask = 0 AIN2 Mask = 0 AIN3 Mask = 0 AIN4 Mask = 0 AIN5 Mask = 0 AIN6 Mask = 0 AIN7 Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set, interrupts generated on the AIN0 Voltage channel are masked out. When this bit is set, interrupts generated on the AIN1 Voltage channel are masked out. When this bit is set, interrupts generated on the AIN2 Voltage channel are masked out. When this bit is set, interrupts generated on the AIN3 Voltage channel are masked out. When this bit is set, interrupts generated on the AIN4 Voltage channel are masked out. When this bit is set, interrupts generated on the AIN5 Voltage channel are masked out. When this bit is set, interrupts generated on the AIN6 Voltage channel are masked out. When this bit is set, interrupts generated on the AIN7 Voltage channel are masked out. -39- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 33. REGISTER 1AH, MASK REGISTER 3 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name FAN0 Mask = 0 FAN1 Mask = 0 FAN2 Mask = 0 FAN3 Mask = 0 FAN4 Mask = 0 FAN5 Mask = 0 FAN6 Mask = 0 FAN7 Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set, interrupts generated on the FAN0 Tach channel are masked out. When this bit is set, interrupts generated on the FAN1 Tach channel are masked out. When this bit is set, interrupts generated on the FAN2 Tach channel are masked out. When this bit is set, interrupts generated on the FAN3 Tach channel are masked out. When this bit is set, interrupts generated on the FAN4 Tach channel are masked out. When this bit is set, interrupts generated on the FAN5 Tach channel are masked out. When this bit is set, interrupts generated on the FAN6 Tach channel are masked out. When this bit is set, interrupts generated on the FAN7 Tach channel are masked out. TABLE 34. REGISTER 1BH, MASK REGISTER 4 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name Int Temp Mask = 0 VBAT Mask = 0 AIN8 Mask = 0 THERM Mask = 0 AFC Mask = 0 Unused CI Mask = 0 GPIO16 Mask = 0 R/W R/W R/W R/W R/W R/W R R/W R/W Description When this bit is set, interrupts generated on the Int Temp channel are masked out. When this bit is set, interrupts generated on the VBAT Voltage channel are masked out. When this bit is set, interrupts generated on the AIN8 Voltage channel are masked out. When this bit is set, interrupts generated from THERM events are masked out. When this bit is set, interrupts generated from Automatic Fan Control events are masked out. Unused. Will read back 0. When this bit is set, interrupts generated by the Chassis Intrusion input are masked out. When this bit is set, interrupts generated on the GPIO16 channel are masked out. -40- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 35. REGISTER 1CH, MASK REGISTER 5 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name GPIO0 Mask = 0 GPIO1 Mask = 0 GPIO2 Mask = 0 GPIO3 Mask = 0 GPIO4 Mask = 0 GPIO5 Mask = 0 GPIO6 Mask = 0 GPIO7 Mask = 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set, interrupts generated on the GPIO0 channel are masked out. When this bit is set, interrupts generated on the GPIO1 channel are masked out. When this bit is set, interrupts generated on the GPIO2 channel are masked out. When this bit is set, interrupts generated on the GPIO3 channel are masked out. When this bit is set, interrupts generated on the GPIO4 channel are masked out. When this bit is set, interrupts generated on the GPIO5 channel are masked out. When this bit is set, interrupts generated on the GPIO6 channel are masked out. When this bit is set, interrupts generated on the GPIO7 channel are masked out. TABLE 36. REGISTER 1DH, MASK REGISTER 6 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name GPIO8 Mask = 0 GPIO9 Mask = 0 GPIO10 Mask GPIO11Mask GPIO12 Mask GPIO13 Mask GPIO14 Mask GPIO15 Mask =0 =0 =0 =0 =0 =0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set, interrupts generated on the GPIO8 channel are masked out. When this bit is set, interrupts generated on the GPIO9 channel are masked out. When this bit is set, interrupts generated on the GPIO10 channel are masked out. When this bit is set, interrupts generated on the GPIO11 channel are masked out. When this bit is set, interrupts generated on the GPIO12 channel are masked out. When this bit is set, interrupts generated on the GPIO13 channel are masked out. When this bit is set, interrupts generated on the GPIO14 channel are masked out. When this bit is set, interrupts generated on the GPIO15 channel are masked out. REV. PrP -41- PRELIMINARY TECHNICAL DATA ADM1026 TABLE 37. REGISTER 1EH, INT TEMP OFFSET (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the Offset Value for the Internal Temperature Channel. A 2's complement number can be written to this register which is then `added' to the measured result before it is stored or compared to limits. In this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change, for whatever reason, for instance from one chassis to another, if the measurement point is moved, if a plug-in card is inserted or removed, etc. (POWER-ON DEFAULT 00H) 7-0 Int Temp Offset TABLE 38. REGISTER 1FH, INT TEMP MEASURED VALUE Bit Name R/W R Description This register contains the measured value of the Internal Temperature Channel. 7-0 Int Temp Value TABLE 39. REGISTER 20H, STATUS REGISTER 1 (POWER-ON DEFAULT 00H) Bit 0 Name Ext1 Temp Status = 0 R/W R Description 1, if Ext1 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of Ext1 temp readings exceeding the Ext1 THERM limit. This bit is also set (once only) if THERM mode is disengaged as a result of Ext1 temp readings going 5 oC below Ext1 THERM limit. 1, if Ext 2 Value (or AIN9 if in voltage measurement mode) is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of Ext2 temp readings exceeding the Ext2 THERM limit. This bit is also set (once only) if THERM mode is disengaged as a result of Ext2 temp readings going 5oC below Ext2 THERM limit. 1, if 3.3VSTBY Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if 3.3VMAIN Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if +5V Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if VCCP Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if +12V Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if -12V Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1 Ext 2 Temp /AIN9 Status = 0 R 2 3 4 5 6 7 3.3VSTBY Status = 0 3.3VMAIN Status = 0 +5V Status = 0 VCCP Status = 0 +12V Status = 0 -12V Status = 0 R R R R R R -42- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 40. REGISTER 21H, STATUS REGISTER 2 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name AIN0 Status = 0 AIN1 Status = 0 AIN2 Status = 0 AIN3 Status = 0 AIN4 Status = 0 AIN5 Status = 0 AIN6 Status = 0 AIN7 Status = 0 R/W R R R R R R R R Description 1, if AIN0 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if AIN1 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if AIN2 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if AIN3 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if AIN4 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if AIN5 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if AIN6 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if AIN7 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. TABLE 41. REGISTER 22H, STATUS REGISTER 3 (POWER-ON DEFAULT 00H) Bit 0 1 2 3 4 5 6 7 Name FAN0 Status = 0 FAN1 Status = 0 FAN2 Status = 0 FAN3 Status = 0 FAN4 Status = 0 FAN5 Status = 0 FAN6 Status = 0 FAN7 Status = 0 R/W R R R R R R R R Description 1, if FAN0 Value is above the High Limit on the previous conversion cycle, 0 otherwise. 1, if FAN1 Value is above the High Limit on the previous conversion cycle, 0 otherwise. 1, if FAN2 Value is above the High Limit on the previous conversion cycle, 0 otherwise. 1, if FAN3 Value is above the High Limit on the previous conversion cycle, 0 otherwise. 1, if FAN4 Value is above the High Limit on the previous conversion cycle, 0 otherwise. 1, if FAN5 Value is above the High Limit on the previous conversion cycle, 0 otherwise. 1, if FAN6 Value is above the High Limit on the previous conversion cycle, 0 otherwise. 1, if FAN7 Value is above the High Limit on the previous conversion cycle, 0 otherwise. REV. PrP -43- PRELIMINARY TECHNICAL DATA ADM1026 TABLE 42. REGISTER 23H STATUS REGISTER 4 POWER-ON DEFAULT 00H Bit 0 Name Int Temp Status = 0 R/W R Description 1, if Int Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of Int temp readings exceeding the Int THERM limit. This bit is also set (once only) if THERM mode is disengaged as a result of Int temp readings going 5oC below Int THERM limit. 1, if VBAT Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. 1, if AIN8 Value is above the High Limit or below the Low Limit on the previous conversion cycle, 0 otherwise. This bit is set (once only) if a THERM mode is engaged as a result of temperature readings exceeding the THERM limits on any channel. This bit is also set (once only) if THERM mode is disengaged as a result of temperature readings going 5oC below THERM limits on any channel. This bit is set (once only) if the fan turns on when in automatic fan speed control (AFC) mode as a result of a temperature reading exceeding TMIN on any channel. This bit is also set (once only) if the fan turns off when in automatic fan speed control mode. Unused. Will read back 0. This bit latches a Chassis Intrusion event. When GPIO16 is configured as an input , this bit is set when GPIO16 is asserted. ("asserted" may be active-high or active-low depending on setting in GPIO Configuration Register). When GPIO16 is configured as an output, setting this bit asserts GPIO16. ("asserted" may be active-high or active-low depending on setting in GPIO Configuration Register). 1 2 3 VBAT Status = 0 AIN8 Status = 0 THERM Status = 0 R R R 4 AFC Status = 0 R 5 6 7 Unused CI Status = 0 GPIO16 Status = 0 R R R R/W -44- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 43. REGISTER 24H, STATUS REGISTER 5 (POWER-ON DEFAULT 00H) Bit 0 Name GPIO0 Status = 0 R/W R Description When GPIO0 is configured as an input , this bit is set when GPIO0 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 1 in GPIO Configuration Register 1). R/W* When GPIO0 is configured as an output, setting this bit asserts GPIO0. ("asserted" may be active-high or active-low depending on setting of bit 1 in GPIO Configuration Register 1). When GPIO1 is configured as an input , this bit is set when GPIO1 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 3 in GPIO Configuration Register 1). R/W* When GPIO1 is configured as an output, setting this bit asserts GPIO1. ("asserted" may be active-high or active-low depending on setting of bit 3 in GPIO Configuration Register 1). When GPIO2 is configured as an input , this bit is set when GPIO2 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 5 in GPIO Configuration Register 1). R/W* When GPIO2 is configured as an output, setting this bit asserts GPIO2. ("asserted" may be active-high or active-low depending on setting of bit 5 in GPIO Configuration Register 1). When GPIO3 is configured as an input , this bit is set when GPIO3 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 7 in GPIO Configuration Register 1). R/W* When GPIO3 is configured as an output, setting this bit asserts GPIO3. ("asserted" may be active-high or active-low depending on setting of bit 7 in GPIO Configuration Register 1). When GPIO4 is configured as an input , this bit is set when GPIO4 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 1 in GPIO Configuration Register 2). R/W* When GPIO4 is configured as an output, setting this bit asserts GPIO4. ("asserted" may be active-high or active-low depending on setting of bit 1 in GPIO Configuration Register 2). When GPIO5 is configured as an input , this bit is set when GPIO5 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 3 in GPIO Configuration Register 2). R/W* When GPIO5 is configured as an output, setting this bit asserts GPIO5. ("asserted" may be active-high or active-low depending on setting of bit 3 in GPIO Configuration Register 2). When GPIO6 is configured as an input , this bit is set when GPIO6 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 5 in GPIO Configuration Register 2). When GPIO6 is configured as an output, setting this bit asserts GPIO6. ("asserted" may be active-high or active-low depending on setting of bit 5 in GPIO Configuration Register 2). 1 GPIO1 Status = 0 R 2 GPIO2 Status = 0 R 3 GPIO3 Status = 0 R 4 GPIO4 Status = 0 R 5 GPIO5 Status = 0 R 6 GPIO6 Status = 0 R R/W 7 GPIO7 Status = 0 R When GPIO7 is configured as an input , this bit is set when GPIO7 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 7 in GPIO Configuration Register 2). R/W* When GPIO7 is configured as an output, setting this bit asserts GPIO7. ("asserted" may be active-high or active-low depending on setting of bit 7 in GPIO Configuration Register 2). *Note: GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise. REV. PrP -45- PRELIMINARY TECHNICAL DATA ADM1026 TABLE 44. REGISTER 25H, STATUS REGISTER 6 (POWER-ON DEFAULT 00H) Bit 0 Name GPIO8 Status = 0 R/W R Description When GPIO8 is configured as an input , this bit is set when GPIO8 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 1 in GPIO Configuration Register 3). R/W* When GPIO8 is configured as an output, setting this bit asserts GPIO8. ("asserted" may be active-high or active-low depending on setting of bit 1 in GPIO Configuration Register 3). When GPIO9 is configured as an input , this bit is set when GPIO9 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 3 in GPIO Configuration Register 3). R/W* When GPIO9 is configured as an output, setting this bit asserts GPIO9. ("asserted" may be active-high or active-low depending on setting of bit 3 in GPIO Configuration Register 3). When GPIO10 is configured as an input , this bit is set when GPIO10 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 5 in GPIO Configuration Register 3). R/W* When GPIO10 is configured as an output, setting this bit asserts GPIO10. ("asserted" may be active-high or active-low depending on setting of bit 5 in GPIO Configuration Register 3). When GPIO11 is configured as an input , this bit is set when GPIO11 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 7 in GPIO Configuration Register 3). R/W* When GPIO11 is configured as an output, setting this bit asserts GPIO11. ("asserted" may be active-high or active-low depending on setting of bit 7 in GPIO Configuration Register 3). When GPIO12 is configured as an input , this bit is set when GPIO12 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 1 in GPIO Configuration Register 4). R/W* When GPIO12 is configured as an output, setting this bit asserts GPIO12. ("asserted" may be active-high or active-low depending on setting of bit 1 in GPIO Configuration Register 4). When GPIO13 is configured as an input , this bit is set when GPIO13 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 3 in GPIO Configuration Register 4). R/W* When GPIO13 is configured as an output, setting this bit asserts GPIO13. ("asserted" may be active-high or active-low depending on setting of bit 3 in GPIO Configuration Register 4). When GPIO14 is configured as an input , this bit is set when GPIO14 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 5 in GPIO Configuration Register 4). R/W* When GPIO14 is configured as an output, setting this bit asserts GPIO14. ("asserted" may be active-high or active-low depending on setting of bit 5 in GPIO Configuration Register 4). When GPIO15 is configured as an input , this bit is set when GPIO15 is asserted. ("asserted" may be active-high or active-low depending on setting of bit 7 in GPIO Configuration Register 4). R/W* When GPIO14 is configured as an output, setting this bit asserts GPIO14. ("asserted" may be active-high or active-low depending on setting of bit 7 in GPIO Configuration Register 4). R R R R R R 1 GPIO9 Status = 0 R 2 GPIO10 Status =0 3 GPIO11 Status =0 4 GPIO12 Status =0 5 GPIO13 Status =0 6 GPIO14 Status =0 7 GPIO15 Status =0 *Note: GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise. -46- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 45. REGISTER 26H, VBAT MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the VBAT analog input channel. 7-0 VBAT Value TABLE 46. REGISTER 27H, AIN8 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the AIN8 analog input channel. 7-0 AIN8 Value TABLE 47. REGISTER 28H, EXT1 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the Ext1 Temp channel. 7-0 Ext1 Value TABLE 48. REGISTER 29H, EXT2 / AIN9 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the Ext2 Temp / AIN9 channel depending on which one is configured. 7-0 Ext2 Temp/AIN9 Value TABLE 49. REGISTER 2AH, 3.3VSTBY MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the 3.3VSTBY voltage 7-0 3.3VSTBY Value TABLE 50. REGISTER 2BH, 3.3VMAIN MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the 3.3VMAIN voltage 7-0 3.3VMAIN Value TABLE 51. REGISTER 2CH, +5V MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the +5V analog input channel 7-0 +5V Value TABLE 52. REGISTER 2DH, VCCP MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the VCCP analog input channel 7-0 VCCP Value TABLE 53. REGISTER 2EH, +12V MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the +12V analog input channel 7-0 +12V Value TABLE 54. REGISTER 2FH, -12V MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the -12V analog input channel 7-0 -12V Value TABLE 55. REGISTER 30H, AIN0 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the AIN0 analog input channel. -47- 7-0 AIN0 Value REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 56. REGISTER 31H, AIN1 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the AIN1 analog input channel. 7-0 AIN1 Value TABLE 57. REGISTER 32H, AIN2 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the AIN2 analog input channel. 7-0 AIN2 Value TABLE 58. REGISTER 33H, AIN3 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the AIN3 analog input channel. 7-0 AIN3 Value TABLE 59. REGISTER 34H, AIN4 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the AIN4 analog input channel. 7-0 AIN4 Value TABLE 60. REGISTER 35H, AIN5 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the AIN5 analog input channel. 7-0 AIN5 Value TABLE 61. REGISTER 36H, AIN6 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the AIN6 analog input channel. 7-0 AIN6 Value TABLE 62. REGISTER 37H, AIN7 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the AIN7 analog input channel. 7-0 AIN7 Value TABLE 63. REGISTER 38H, FAN0 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the FAN0 tach input channel. 7-0 FAN0 Value TABLE 64. REGISTER 39H, FAN1 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the FAN1 tach input channel. 7-0 FAN1 Value TABLE 65. REGISTER 3AH, FAN2 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the FAN2 tach input channel. 7-0 FAN2 Value TABLE 66. REGISTER 3BH, FAN3 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the FAN3 tach input channel. 7-0 FAN3 Value -48- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 67. REGISTER 3CH, FAN4 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the FAN4 tach input channel. 7-0 FAN4 Value TABLE 68. REGISTER 3DH, FAN5 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the FAN5 tach input channel. 7-0 FAN5 Value TABLE 69. REGISTER 3EH, FAN6 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the FAN6 tach input channel. 7-0 FAN6 Value TABLE 70. REGISTER 3FH, FAN7 MEASURED VALUE (POWER-ON DEFAULT 00H) Bit Name R/W R Description This register contains the measured value of the FAN7 tach input channel. 7-0 FAN7 Value TABLE 71. REGISTER 40H, EXT1 HIGH LIMIT (POWER-ON DEFAULT 64H/100OC) Bit Name R/W R/W Description This register contains the high limit of the Ext1 Temp channel. 7-0 Ext1 High Limit TABLE 72. REGISTER 41H, EXT2 / AIN9 HIGH LIMIT (POWER-ON DEFAULT 64H/100OC) Bit Name R/W R/W Description This register contains the high limit of the Ext2 Temp / AIN9 channel depending on which one is configured. 7-0 Ext2 Temp /AIN9 High Limit TABLE 73. REGISTER 42H, 3.3VSTBY HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the 3.3VSTBY analog input channel 7-0 3.3VSTBY High Limit TABLE 74. REGISTER 43H, 3.3VMAIN HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the 3.3VMAIN analog input channel 7-0 3.3VMAIN High Limit TABLE 75. REGISTER 44H, +5V HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the +5V analog input channel 7-0 +5V High Limit TABLE 76. REGISTER 45H, VCCP HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the VCCP analog input channel 7-0 VCCP High Limit TABLE 77. REGISTER 46H, +12V HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the +12V analog input channel -49- 7-0 +12V High Limit REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 78. REGISTER 47H, -12V HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the -12V analog input channel 7-0 -12V High Limit TABLE 79. REGISTER 48H, EXT1 LOW LIMIT (POWER-ON DEFAULT 80H) Bit Name R/W R/W Description This register contains the low limit of the Ext1 Temp channel. 7-0 Ext1 Low Limit TABLE 80. REGISTER 49H, EXT2 / AIN9 LOW LIMIT (POWER-ON DEFAULT 80H) Bit Name R/W R/W Description This register contains the low limit of the Ext2 Temp / AIN9 channel depending on which one is configured. 7-0 Ext2 Temp /AIN9 Low Limit TABLE 81. REGISTER 4AH, 3.3VSTBY LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the 3.3VSTBY analog input channel 7-0 3.3VSTBY Low Limit TABLE 82. REGISTER 4BH, 3.3VMAIN LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the 3.3VMAIN analog input channel 7-0 3.3VMAIN Low Limit TABLE 83. REGISTER 4CH, +5V LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the +5V analog input channel 7-0 +5V Low Limit TABLE 84. REGISTER 4DH, VCCP LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the VCCP analog input channel 7-0 VCCP Low Limit TABLE 85. REGISTER 4EH, +12V LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the +12V analog input channel 7-0 +12V Low Limit TABLE 86. REGISTER 4FH, -12V LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the -12V analog input channel 7-0 -12V Low Limit TABLE 87. REGISTER 50H, AIN0 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the AIN0 analog input channel. 7-0 AIN0 High Limit TABLE 88. REGISTER 51H, AIN1 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the AIN1 analog input channel -50- REV. PrP 7-0 AIN1 High Limit PRELIMINARY TECHNICAL DATA ADM1026 TABLE 89. REGISTER 52H, AIN2 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the AIN2 analog input channel 7-0 AIN2 High Limit TABLE 90. REGISTER 53H, AIN3 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the AIN3 analog input channel 7-0 AIN3 High Limit TABLE 91. REGISTER 54H, AIN4 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the AIN4 analog input channel 7-0 AIN4 High Limit TABLE 92. REGISTER 55H, AIN5 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the AIN5 analog input channel 7-0 AIN5 High Limit TABLE 93. REGISTER 56H, AIN6 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the AIN6 analog input channel 7-0 AIN6 High Limit TABLE 94. REGISTER 57H, AIN7 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the AIN7 analog input channel 7-0 AIN7 High Limit TABLE 95. REGISTER 58H, AIN0 LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the AIN0 analog input channel. 7-0 AIN0 Low Limit TABLE 96. REGISTER 59H, AIN1 LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the AIN1 analog input channel 7-0 AIN1 Low Limit TABLE 97. REGISTER 5AH, AIN2 LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the AIN2 analog input channel 7-0 AIN2 Low Limit TABLE 98. REGISTER 5BH, AIN3 LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the AIN3 analog input channel 7-0 AIN3 Low Limit TABLE 99. REGISTER 5CH, AIN4 LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the AIN4 analog input channel 7-0 AIN4 Low Limit REV. PrP -51- PRELIMINARY TECHNICAL DATA ADM1026 TABLE 100. REGISTER 5DH, AIN5 LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the AIN5 analog input channel 7-0 AIN5 Low Limit TABLE 101. REGISTER 5EH, AIN6 LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the AIN6 analog input channel 7-0 AIN6 Low Limit TABLE 102. REGISTER 5FH, AIN7 LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the AIN7 analog input channel 7-0 AIN7 Low Limit TABLE 103. REGISTER 60H, FAN0 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the FAN0 tach channel. 7-0 FAN0 High Limit TABLE 104. REGISTER 61H, FAN1 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the FAN1 tach channel 7-0 FAN1 High Limit TABLE 105. REGISTER 62H, FAN2 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the FAN2 tach channel 7-0 FAN2 High Limit TABLE 106. REGISTER 63H, FAN3 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the FAN3 tach channel 7-0 FAN3 High Limit TABLE 107. REGISTER 64H, FAN4 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the FAN4 tach channel 7-0 FAN4 High Limit TABLE 108. REGISTER 65H, FAN5 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the FAN5 tach channel 7-0 FAN5 High Limit TABLE 109. REGISTER 66H, FAN6 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the FAN6 tach channel 7-0 FAN6 High Limit TABLE 110. REGISTER 67H, FAN7 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the FAN7 tach channel 7-0 FAN7 High Limit -52- REV. PrP PRELIMINARY TECHNICAL DATA ADM1026 TABLE 111. REGISTER 68H, INT TEMP HIGH LIMIT (POWER-ON DEFAULT 50H (80OC) ) Bit Name R/W R/W Description This register contains the high limit of the internal temperature channel. 7-0 Int Temp High Limit TABLE 112. REGISTER 69H, INT TEMP LOW LIMIT (POWER-ON DEFAULT 80H) Bit Name R/W R/W Description This register contains the low limit of the internal temperature channel 7-0 Int Temp Low Limit TABLE 113. REGISTER 6AH, VBAT HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the VBAT analog input channel 7-0 VBAT High Limit TABLE 114. REGISTER 6BH, VBAT LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the VBAT analog input channel 7-0 VBAT Low Limit TABLE 115. REGISTER 6CH, AIN8 HIGH LIMIT (POWER-ON DEFAULT FFH) Bit Name R/W R/W Description This register contains the high limit of the AIN8 analog input channel 7-0 AIN8 High Limit TABLE 116. REGISTER 6DH, AIN8 LOW LIMIT (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the low limit of the AIN8 analog input channel 7-0 AIN8 Low Limit TABLE 117. REGISTER 6EH, EXT1 TEMP OFFSET (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the Offset Value for the External 1 Temperature Channel. A 2's complement number can be written to this register which is then `added' to the measured result before it is stored or compared to limits. In this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change, for whatever reason, for instance from one chassis to another, if the measurement point is moved, if a plug-in card is inserted or removed, etc. 7-0 Ext1 Temp Offset TABLE 118. REGISTER 6FH, EXT2 TEMP OFFSET (POWER-ON DEFAULT 00H) Bit Name R/W R/W Description This register contains the Offset Value for the External 2 Temperature Channel. A 2's complement number can be written to this register which is then `added' to the measured result before it is stored or compared to limits. In this way a sort of one-point calibration can be done whereby the whole transfer function of the channel can be moved up or down. From a software point of view this may be a very simple method to vary the characteristics of the measurement channel if the thermal characteristics change, for whatever reason, for instance from one chassis to another, if the measurement point is moved, if a plug-in card is inserted or removed, etc. 7-0 Ext2 Temp Offset REV. PrP -53- PRELIMINARY TECHNICAL DATA ADM1026 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.354 (9.00) BSC 0.276 (7.00) BSC PIN 1 (1.00) (0.60) 0.02 (0.50) BSC (0.22) 0o MIN 0.01 (0.25) 0.063 (1.60) 0.055 (1.40) 0o 7o 0.006 (0.15) 0.002 (0.05) 48-Pin LQFP Package (ST-48) 0.276 (7.0 0) BSC 0.354 (9.0 0) BSC -54- REV. PrP |
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